Number systems
- Place values
- binary 2k, octal 8k, hex 16k
- To decimal
- Σ dk·bk
- From decimal
- divide by the base, read the remainders bottom-up
- Hex ↔ binary
- one hex digit = 4 bits
- Two’s complement
- invert the bits and add 1
Digital Electronics: cram pack
Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.
1Formulas and methods
Digital logic: gates, K-maps & flip-flops
- Basic gates
- A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
- Boolean rules
- X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
- De Morgan
- (X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
- Karnaugh map order
- 00, 01, 11, 10 (Gray code)
- Group of 2ᵏ cells
- loses k variables
- 4-to-1 multiplexer
- F = A′B′I0 + A′BI1 + AB′I2 + ABI3
- Flip-flops
- D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
- Counters
- n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
- Ripple counter
- fmax = 1/(n·tpd)
- Ring and Johnson counters
- n and 2n states
Method
- For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
- For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
- Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
- For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
Data acquisition & sampling
- Nyquist criterion
- fs > 2·fmax, fN = fs/2
- Alias frequency
- fa = |f − k·fs|, k = round(f/fs)
- Step size
- 1 LSB = VFSR/2ᴺ
- Quantisation error (rounding)
- ±½ LSB
- Truncating ADC code
- D = ⌊Vin/LSB⌋
- Bits for a resolution r
- 2ᴺ ≥ span/r
- Ideal SQNR, full-scale sine
- SQNR = 6.02·N + 1.76 dB
- Data rate
- channels × fs × N bit/s
- Multiplexed ADC
- fs = 1/(n·(tc + tset))
- UART
- Tb = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
- Baud rate divider
- baud = fclk/(16·D)
Method
- Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
- For sampling questions, compare each frequency with fs/2; a higher frequency appears at fa = |f − k·fs| with the nearest multiple of fs.
- For resolution questions, find 1 LSB = VFSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
- For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.
2Practice problems
1.Number systemsMedium
Set the bits so they store −104 in 8-bit two's complement. Read as an unsigned number, what is the pattern's value U?
N = −1048 bit
U =
2.Number systemsHard
What is the largest unsigned integer N that fits in 32 bits?
32 bit
N =
3.Digital logic: gates, K-maps & flip-flopsMedium
Simplify F = AB + AC′ + A′B′C + A′B′C′ to its minimal sum-of-products form. How many literals L does the simplified expression contain?
F = AB + AC′ + A′B′C + A′B′C′
L =
4.Digital logic: gates, K-maps & flip-flopsHard
A positive-edge-triggered D flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.
Q₀ = 0D
- 1clock edge 1
- 2clock edge 2
- 3clock edge 3
- 4clock edge 4
- 5clock edge 5
- 6clock edge 6
- 7clock edge 7
5.Data acquisition & samplingMedium
A 5.4 kHz sine wave is sampled at 4 kHz without an anti-aliasing filter. At which frequency fa does it appear in the samples? Give it in Hz.
f = 5.4 kHzfs = 4 kHz
fa = Hz
6.Data acquisition & samplingHard
A microcontroller with a 24 MHz clock sets its UART baud rate as fclk/(16·D), with D a whole number rounded to the nearest value. The target is 57600 baud. Find the percentage error of the real baud rate (positive when it is too fast).
fclk = 24 MHztarget = 57600 Bd
e = %
3Solutions
1.Number systems
Answer: U = 152
Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.
Invert and add one
104 = 0110 1000
inverted: 1001 0111
+1 → 1001 1000
Read it as unsigned
1001 1000₂ = 256 − 104 = 152
Answer
U = 152
2.Number systems
Answer: N = 4.295 × 10⁹
Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.
Largest value
232 − 1 = 4294967295
Answer
N = 4294967295
3.Digital logic: gates, K-maps & flip-flops
Answer: L = 6
Boolean algebra: the rules that simplify expressions are X + X′ = 1 and X·X′ = 0, X + X = X, absorption X + X·Y = X, the combining rule X·Y + X·Y′ = X, X + X′Y = X + Y and the consensus theorem XY + X′Z + YZ = XY + X′Z. De Morgan's laws turn (X·Y)′ into X′ + Y′ and (X + Y)′ into X′·Y′. A Karnaugh map applies these rules graphically: every group of two neighbouring cells is one use of XY + XY′ = X.
Minterms of the expression
AB → m(6, 7)
AC′ → m(4, 6)
A′B′C → m(1)
A′B′C′ → m(0)
Group and read off
F = B′C′ + A′B′ + AB
Count the literals
L = 6
Answer
L = 6
Another grouping of the same size exists; it has the same number of literals.
4.Digital logic: gates, K-maps & flip-flops
Answer: clock edge 6
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
Q after every edge
A D flip-flop copies D at each rising edge: Q⁺ = D.
1: D = 0 → Q = 0
2: D = 0 → Q = 0
3: D = 0 → Q = 0
4: D = 1 → Q = 1
5: D = 1 → Q = 1
6: D = 0 → Q = 0
7: D = 1 → Q = 1
First change from 1 to 0
clock edge 6
Answer
clock edge 6
5.Data acquisition & sampling
Answer: fa = 1400 Hz
Sampling: an ADC measures the signal fs times per second. By the Nyquist–Shannon theorem a frequency f is captured correctly only while f < fs/2, the Nyquist (folding) frequency, so the sampling rate must exceed twice the highest signal frequency. A higher frequency is not lost: it shows up as an alias at fa = |f − k·fs|, with the whole number k that brings the result between 0 and fs/2. The samples cannot tell the two apart, so an analogue anti-aliasing filter must remove everything above fs/2 before the ADC.
Nyquist frequency
fs/2 = 2 kHz < f = 5.4 kHz
Nearest multiple of the sampling rate
k = round(5400/4000) = 1
Alias frequency
fa = |5400 − 1·4000| = 1400 Hz
Answer
fa = 1400 Hz
The dashed curve in the figure is the alias: it passes through exactly the same samples.
6.Data acquisition & sampling
Answer: e = 0.1603 %
UART: an asynchronous serial link sends each byte as a frame: one start bit (low), the data bits, an optional parity bit and one or two stop bits (high). The baud rate is the number of bits per second, so one bit lasts Tb = 1/baud and a frame of n bits lasts n/baud. The common 8N1 format has 10 bits per byte. The baud generator divides the clock: baud = fclk/(16·D) with a whole number D, so the real baud rate differs slightly from the target; an error below about 2 % is usually acceptable.
Divider
D = 24·10⁶/(16·57600) = 26.04 → 26
Real baud rate
24·10⁶/(16·26) = 57692 Bd
Error
(57692 − 57600)/57600·100 = 0.1603 %
Answer
e = 0.1603 %
An error below about 2 % is usually acceptable.
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