Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

New problemsBack to the course

In the print window, choose “Save as PDF” to keep a copy on your device.

1Formulas and methods

Number systems

Place values
binary 2k, octal 8k, hex 16k
To decimal
Σ dk·bk
From decimal
divide by the base, read the remainders bottom-up
Hex ↔ binary
one hex digit = 4 bits
Two’s complement
invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion
fs > 2·fmax, fN = fs/2
Alias frequency
fa = |f − k·fs|, k = round(f/fs)
Step size
1 LSB = VFSR/2ᴺ
Quantisation error (rounding)
±½ LSB
Truncating ADC code
D = ⌊Vin/LSB⌋
Bits for a resolution r
2ᴺ ≥ span/r
Ideal SQNR, full-scale sine
SQNR = 6.02·N + 1.76 dB
Data rate
channels × fs × N bit/s
Multiplexed ADC
fs = 1/(n·(tc + tset))
UART
Tb = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider
baud = fclk/(16·D)

Method

  1. Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
  2. For sampling questions, compare each frequency with fs/2; a higher frequency appears at fa = |f − k·fs| with the nearest multiple of fs.
  3. For resolution questions, find 1 LSB = VFSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
  4. For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium
8-bit two's complement?−128?64?32?16?8?4?2?1

Write −107 as an 8-bit two's complement pattern. Read the pattern as an unsigned binary number: what is its value U in decimal?

N = −1078 bit
U =
2.Number systemsHard
click the bits to set them012806403201608040201

Set the bits to the 8-bit result of 0001 0111 OR 1101 0001. What is the result's value R in decimal?

0001 0111OR1101 0001
R =
3.Digital logic: gates, K-maps & flip-flopsMedium
ABC00011110011011031214050716

Use the Karnaugh map to find the minimal product-of-sums (POS) form of F(A, B, C) = Σm(0, 1, 2, 4, 6). How many sum terms (factors) N does it have?

F(A, B, C) = Σm(0, 1, 2, 4, 6)
N =
4.Digital logic: gates, K-maps & flip-flopsHard
ABCD0001111000011110X0111312X4150716X12013015X141809111010

Find the minimal SOP form of F(A, B, C, D) = Σm(1, 2, 3, 5, 6, 8, 11) + d(0, 4, 12, 14), where d marks the don't-care conditions. How many literals L does it contain?

F(A, B, C, D) = Σm(1, 2, 3, 5, 6, 8, 11) + d(0, 4, 12, 14)
L =
5.Data acquisition & samplingMedium
Vin​N = 24VFSR​2ᴺ − 101 LSB

Find the ideal signal-to-quantisation-noise ratio SQNR of a 24-bit ADC for a full-scale sine wave.

N = 24
SQNR = dB
6.Data acquisition & samplingHard
1216⋮16 ch∿01tc​ = 20 µstset​ = 5 µsfs​ = ?

A 16-channel multiplexer feeds one ADC. Each conversion takes 20 µs, and after every channel switch the input needs 5 µs to settle. The channels are scanned in turn without pause. Find the sampling rate fs of each channel, in kHz.

n = 16tc = 20 µstset = 5 µs
fs = kHz

3Solutions

1.Number systems

Answer: U = 149

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Invert and add one

107 = 0110 1011
inverted: 1001 0100
+1 → 1001 0101

Read it as unsigned

1001 0101₂ = 256 − 107 = 149

Answer

U = 149
2.Number systems

Answer: R = 215

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Bit by bit

OR gives 1 where at least one bit is 1.

0001 0111
OR 1101 0001
= 1101 0111

Value of the result

1101 0111₂ = 215

Answer

R = 215
3.Digital logic: gates, K-maps & flip-flops

Answer: N = 2

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

ABC00011110011011031214050716

Group the 0s

Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.

(B′ + C′)
(A′ + C′)

Minimal POS form

F = (B′ + C′)(A′ + C′)
N = 2

Answer

N = 2
4.Digital logic: gates, K-maps & flip-flops

Answer: L = 9

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Prime implicants

The largest groups that can be formed from 1s and Xs.

C′D′, BD′, B′CD, A′D′, A′C′, A′B′
ABCD0001111000011110X0111312X4150716X12013015X141809111010

Minimal cover

F = C′D′ + B′CD + A′D′ + A′C′
L = 9

Answer

L = 9
5.Data acquisition & sampling

Answer: SQNR = 146.2 dB

ADC resolution: an N-bit converter divides its full-scale range VFSR into 2ᴺ codes, from 0 to 2ᴺ − 1. One step is 1 LSB = VFSR/2ᴺ: the smallest change the converter can show. A truncating ADC gives the code ⌊Vin/LSB⌋; a rounding ADC is never more than ½ LSB away from the true value, its quantisation error. Every extra bit halves the LSB and adds about 6 dB to the ideal signal-to-quantisation-noise ratio SQNR = 6.02·N + 1.76 dB for a full-scale sine. To reach a resolution r over a span, choose the smallest N with 2ᴺ ≥ span/r.

Ideal SQNR

SQNR = 6.02·24 + 1.76 = 146.2 dB

Answer

SQNR = 146.2 dB
6.Data acquisition & sampling

Answer: fs = 2.5 kHz

Data rates: every channel delivers fs samples per second of N bits, so the raw rate is channels × fs × N bit/s. In memory a sample takes whole bytes (a 12-bit sample is stored in 2 bytes), so the memory for a recording is channels × fs × bytes per sample × time. A multiplexed ADC converts the channels one after another: each conversion (with settling) takes t, so one round of n channels takes n·t and each channel is sampled at 1/(n·t).

Time per channel

20 + 5 = 25 µs

Time per scan

16·25 = 400 µs

Sampling rate per channel

fs = 1/400 µs = 2.5 kHz

Answer

fs = 2.5 kHz

ExamProblems · examproblems.com/courses/digital-electronics