Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

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1Formulas and methods

Number systems

Place values: binary 2^k, octal 8^k, hex 16^k
To decimal: Σ d_k·b^k
From decimal: divide by the base, read the remainders bottom-up
Hex ↔ binary: one hex digit = 4 bits
Two’s complement: invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates: A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules: X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan: (X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order: 00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells: loses k variables
4-to-1 multiplexer: F = A′B′I₀ + A′BI₁ + AB′I₂ + ABI₃
Flip-flops: D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters: n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; f_out = f_clk/N
Ripple counter: f_max = 1/(n·t_pd)
Ring and Johnson counters: n and 2n states

Method

For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion: f_s > 2·f_max, f_N = f_s/2
Alias frequency: f_a = |f − k·f_s|, k = round(f/f_s)
Step size: 1 LSB = V_FSR/2ᴺ
Quantisation error (rounding): ±½ LSB
Truncating ADC code: D = ⌊V_in/LSB⌋
Bits for a resolution r: 2ᴺ ≥ span/r
Ideal SQNR, full-scale sine: SQNR = 6.02·N + 1.76 dB
Data rate: channels × f_s × N bit/s
Multiplexed ADC: f_s = 1/(n·(t_c + t_set))
UART: T_b = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider: baud = f_clk/(16·D)

Method

Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
For sampling questions, compare each frequency with f_s/2; a higher frequency appears at f_a = |f − k·f_s| with the nearest multiple of f_s.
For resolution questions, find 1 LSB = V_FSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium

The 8-bit pattern 1000 1011 stores a signed integer in two's complement. What is its value N in decimal?

1000 10118 bit

N =

2.Number systemsHard

Set the bits to the 8-bit result of 1011 1111 XOR 0010 0101. What is the result's value R in decimal?

1011 1111XOR0010 0101

R =

3.Digital logic: gates, K-maps & flip-flopsMedium

A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = C′, I₁ = 0, I₂ = 0, I₃ = 0. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.

I₀ = C′I₁ = 0I₂ = 0I₃ = 0

N =

4.Digital logic: gates, K-maps & flip-flopsHard

A 4-bit ring counter Q₃Q₂Q₁Q₀ starts at 1100. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀) and Q₃ receives Q₀. Give the state Q = Q₃Q₂Q₁Q₀ as a decimal number after 10 clock edges.

Q₃Q₂Q₁Q₀ = 110010

Q =

5.Data acquisition & samplingMedium

A recorder samples one channel at 2 kHz with a 24-bit ADC. Each sample is stored in whole bytes. Find the memory M needed for a 2 min recording, in MB (1 MB = 10⁶ bytes).

n = 1f_s = 2 kHzN = 24t = 2 min

M = MB

6.Data acquisition & samplingHard

A microcontroller with a 4 MHz clock sets its UART baud rate as f_clk/(16·D), with D a whole number rounded to the nearest value. The target is 9600 baud. Find the percentage error of the real baud rate (positive when it is too fast).

f_clk = 4 MHztarget = 9600 Bd

e = %

3Solutions

1.Number systems

Answer: N = −117

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Add the place values

The other bits keep their normal positive values.

−128 + 8 + 2 + 1 = −117

Answer

N = −117

2.Number systems

Answer: R = 154

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Bit by bit

XOR gives 1 where the two bits differ.

1011 1111

XOR 0010 0101

= 1001 1010

Value of the result

1001 1010₂ = 154

Answer

R = 154

3.Digital logic: gates, K-maps & flip-flops

Answer: N = 1

Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.

Output expression

F = A′B′C′

Rows with F = 1

ABC = 000

N = 1

Answer

N = 1

4.Digital logic: gates, K-maps & flip-flops

Answer: Q = 3

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at f_clk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

State after every edge

1100 → 0110 → 0011 → 1001 → 1100 → 0110 → 0011 → 1001 → 1100 → 0110 → 0011

Decimal value

0011₂ = 3

Answer

Q = 3

5.Data acquisition & sampling

Answer: M = 0.72 MB

Data rates: every channel delivers f_s samples per second of N bits, so the raw rate is channels × f_s × N bit/s. In memory a sample takes whole bytes (a 12-bit sample is stored in 2 bytes), so the memory for a recording is channels × f_s × bytes per sample × time. A multiplexed ADC converts the channels one after another: each conversion (with settling) takes t, so one round of n channels takes n·t and each channel is sampled at 1/(n·t).

Bytes per sample

⌈24/8⌉ = 3 B

Byte rate

1·2000·3 = 6000 B/s

Memory

M = 6000·120 = 720000 B = 0.72 MB

Answer

M = 0.72 MB

6.Data acquisition & sampling

Answer: e = 0.1603 %

UART: an asynchronous serial link sends each byte as a frame: one start bit (low), the data bits, an optional parity bit and one or two stop bits (high). The baud rate is the number of bits per second, so one bit lasts T_b = 1/baud and a frame of n bits lasts n/baud. The common 8N1 format has 10 bits per byte. The baud generator divides the clock: baud = f_clk/(16·D) with a whole number D, so the real baud rate differs slightly from the target; an error below about 2 % is usually acceptable.

Divider

D = 4·10⁶/(16·9600) = 26.04 → 26

Real baud rate

4·10⁶/(16·26) = 9615 Bd

Error

(9615 − 9600)/9600·100 = 0.1603 %

Answer

e = 0.1603 %

An error below about 2 % is usually acceptable.

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