Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

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1Formulas and methods

Number systems

Place values: binary 2^k, octal 8^k, hex 16^k
To decimal: Σ d_k·b^k
From decimal: divide by the base, read the remainders bottom-up
Hex ↔ binary: one hex digit = 4 bits
Two’s complement: invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates: A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules: X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan: (X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order: 00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells: loses k variables
4-to-1 multiplexer: F = A′B′I₀ + A′BI₁ + AB′I₂ + ABI₃
Flip-flops: D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters: n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; f_out = f_clk/N
Ripple counter: f_max = 1/(n·t_pd)
Ring and Johnson counters: n and 2n states

Method

For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion: f_s > 2·f_max, f_N = f_s/2
Alias frequency: f_a = |f − k·f_s|, k = round(f/f_s)
Step size: 1 LSB = V_FSR/2ᴺ
Quantisation error (rounding): ±½ LSB
Truncating ADC code: D = ⌊V_in/LSB⌋
Bits for a resolution r: 2ᴺ ≥ span/r
Ideal SQNR, full-scale sine: SQNR = 6.02·N + 1.76 dB
Data rate: channels × f_s × N bit/s
Multiplexed ADC: f_s = 1/(n·(t_c + t_set))
UART: T_b = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider: baud = f_clk/(16·D)

Method

Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
For sampling questions, compare each frequency with f_s/2; a higher frequency appears at f_a = |f − k·f_s| with the nearest multiple of f_s.
For resolution questions, find 1 LSB = V_FSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium

Set the bits so they store −101 in 8-bit two's complement. Read as an unsigned number, what is the pattern's value U?

N = −1018 bit

U =

2.Number systemsHard

What is the most negative integer N that can be stored in 12-bit two's complement?

12 bit

N =

3.Digital logic: gates, K-maps & flip-flopsMedium

A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = C, I₁ = 1, I₂ = 0, I₃ = C. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.

I₀ = CI₁ = 1I₂ = 0I₃ = C

N =

4.Digital logic: gates, K-maps & flip-flopsHard

A 4-bit shift register Q₃Q₂Q₁Q₀ holds 0010. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀, Q₀ is lost) and the serial input enters Q₃. The serial input is 1, 1, 1, 0, 0 at the 5 edges. Give the final state Q = Q₃Q₂Q₁Q₀ as a decimal number.

Q₃Q₂Q₁Q₀ = 00101, 1, 1, 0, 0

Q =

5.Data acquisition & samplingMedium

A UART sends bytes at 1200 baud in the format 8N2: 8 data bits, no parity and 2 stop bit(s), plus the start bit. Find the largest number of data bytes per second it can transfer.

baud = 1200 Bd8N2

R_B = B/s

6.Data acquisition & samplingHard

A 4-channel multiplexer feeds one ADC. Each conversion takes 2 µs, and after every channel switch the input needs 0.5 µs to settle. The channels are scanned in turn without pause. Find the sampling rate f_s of each channel, in kHz.

n = 4t_c = 2 µst_set = 0.5 µs

f_s = kHz

3Solutions

1.Number systems

Answer: U = 155

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Invert and add one

101 = 0110 0101

inverted: 1001 1010

+1 → 1001 1011

Read it as unsigned

1001 1011₂ = 256 − 101 = 155

Answer

U = 155

2.Number systems

Answer: N = −2048

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Most negative value

−2¹¹ = −2048

Answer

N = −2048

3.Digital logic: gates, K-maps & flip-flops

Answer: N = 4

Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.

Output expression

F = A′B′C + A′B + ABC

Rows with F = 1

ABC = 001, 010, 011, 111

N = 4

Answer

N = 4

4.Digital logic: gates, K-maps & flip-flops

Answer: Q = 3

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at f_clk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

State after every edge

0010 → 1001 → 1100 → 1110 → 0111 → 0011

Decimal value

0011₂ = 3

Answer

Q = 3

5.Data acquisition & sampling

Answer: R_B = 109.1 B/s

UART: an asynchronous serial link sends each byte as a frame: one start bit (low), the data bits, an optional parity bit and one or two stop bits (high). The baud rate is the number of bits per second, so one bit lasts T_b = 1/baud and a frame of n bits lasts n/baud. The common 8N1 format has 10 bits per byte. The baud generator divides the clock: baud = f_clk/(16·D) with a whole number D, so the real baud rate differs slightly from the target; an error below about 2 % is usually acceptable.

Bits per frame

1 + 8 + 0 + 2 = 11

Byte rate

1200/11 = 109.1 B/s

Answer

R_B = 109.1 B/s

6.Data acquisition & sampling

Answer: f_s = 100 kHz

Data rates: every channel delivers f_s samples per second of N bits, so the raw rate is channels × f_s × N bit/s. In memory a sample takes whole bytes (a 12-bit sample is stored in 2 bytes), so the memory for a recording is channels × f_s × bytes per sample × time. A multiplexed ADC converts the channels one after another: each conversion (with settling) takes t, so one round of n channels takes n·t and each channel is sampled at 1/(n·t).

Time per channel

2 + 0.5 = 2.5 µs

Time per scan

4·2.5 = 10 µs

Sampling rate per channel

f_s = 1/10 µs = 100 kHz

Answer

f_s = 100 kHz

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