Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

New problemsBack to the course

In the print window, choose “Save as PDF” to keep a copy on your device.

1Formulas and methods

Number systems

Place values
binary 2k, octal 8k, hex 16k
To decimal
Σ dk·bk
From decimal
divide by the base, read the remainders bottom-up
Hex ↔ binary
one hex digit = 4 bits
Two’s complement
invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion
fs > 2·fmax, fN = fs/2
Alias frequency
fa = |f − k·fs|, k = round(f/fs)
Step size
1 LSB = VFSR/2ᴺ
Quantisation error (rounding)
±½ LSB
Truncating ADC code
D = ⌊Vin/LSB⌋
Bits for a resolution r
2ᴺ ≥ span/r
Ideal SQNR, full-scale sine
SQNR = 6.02·N + 1.76 dB
Data rate
channels × fs × N bit/s
Multiplexed ADC
fs = 1/(n·(tc + tset))
UART
Tb = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider
baud = fclk/(16·D)

Method

  1. Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
  2. For sampling questions, compare each frequency with fs/2; a higher frequency appears at fa = |f − k·fs| with the nearest multiple of fs.
  3. For resolution questions, find 1 LSB = VFSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
  4. For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium
8-bit two's complement?−128?64?32?16?8?4?2?1

Write −49 as an 8-bit two's complement pattern. Read the pattern as an unsigned binary number: what is its value U in decimal?

N = −498 bit
U =
2.Number systemsHard
click the bits to set them012806403201608040201

Set the bits to the 8-bit result of 1000 1110 << 1. What is the result's value R in decimal?

1000 1110<< 1
R =
3.Digital logic: gates, K-maps & flip-flopsMedium
ABC000111100101324576

Simplify F = BC + ABC + A′C to its minimal sum-of-products form. How many literals L does the simplified expression contain?

F = BC + ABC + A′C
L =
4.Digital logic: gates, K-maps & flip-flopsHard
ABCD0001111000011110X0X1130204150716112113115014X809011110

Find the minimal SOP form of F(A, B, C, D) = Σm(3, 5, 6, 10, 12, 13, 15) + d(0, 1, 8), where d marks the don't-care conditions. How many product terms N does it have?

F(A, B, C, D) = Σm(3, 5, 6, 10, 12, 13, 15) + d(0, 1, 8)
N =
5.Data acquisition & samplingMedium
tTs​ = 1/fs​f = 135 kHzfs​ = 100 kHz

A 135 kHz sine wave is sampled at 100 kHz without an anti-aliasing filter. At which frequency fa does it appear in the samples? Give it in kHz.

f = 135 kHzfs = 100 kHz
fa = kHz
6.Data acquisition & samplingHard
SD0​D1​D2​D3​D4​D5​D6​D7​1/fbaud​10 MHz / (16·D)

A microcontroller with a 10 MHz clock sets its UART baud rate as fclk/(16·D), with D a whole number rounded to the nearest value. The target is 2400 baud. Find the percentage error of the real baud rate (positive when it is too fast).

fclk = 10 MHztarget = 2400 Bd
e = %

3Solutions

1.Number systems

Answer: U = 207

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Invert and add one

49 = 0011 0001
inverted: 1100 1110
+1 → 1100 1111

Read it as unsigned

1100 1111₂ = 256 − 49 = 207

Answer

U = 207
2.Number systems

Answer: R = 28

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Bit by bit

Shifting left by 1 moves every bit 1 places to the left; bits that fall off the left end are lost and zeros come in on the right.

1000 1110 << 1
= 0001 1100

Value of the result

0001 1100₂ = 28

Answer

R = 28
3.Digital logic: gates, K-maps & flip-flops

Answer: L = 4

Boolean algebra: the rules that simplify expressions are X + X′ = 1 and X·X′ = 0, X + X = X, absorption X + X·Y = X, the combining rule X·Y + X·Y′ = X, X + X′Y = X + Y and the consensus theorem XY + X′Z + YZ = XY + X′Z. De Morgan's laws turn (X·Y)′ into X′ + Y′ and (X + Y)′ into X′·Y′. A Karnaugh map applies these rules graphically: every group of two neighbouring cells is one use of XY + XY′ = X.

Minterms of the expression

BC → m(3, 7)
ABC → m(7)
A′C → m(1, 3)
ABC00011110010011130204051706

Group and read off

F = BC + A′C

Count the literals

L = 4

Answer

L = 4
4.Digital logic: gates, K-maps & flip-flops

Answer: N = 6

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Prime implicants

The largest groups that can be formed from 1s and Xs.

BC′D, A′C′D, AC′D′, A′B′D, AB′D′, ABD, ABC′, A′BCD′
ABCD0001111000011110X0X1130204150716112113115014X809011110

Minimal cover

F = BC′D + AC′D′ + A′B′D + AB′D′ + ABD + A′BCD′
N = 6

Answer

N = 6

Another grouping of the same size exists; it has the same number of terms and literals.

5.Data acquisition & sampling

Answer: fa = 35 kHz

Sampling: an ADC measures the signal fs times per second. By the Nyquist–Shannon theorem a frequency f is captured correctly only while f < fs/2, the Nyquist (folding) frequency, so the sampling rate must exceed twice the highest signal frequency. A higher frequency is not lost: it shows up as an alias at fa = |f − k·fs|, with the whole number k that brings the result between 0 and fs/2. The samples cannot tell the two apart, so an analogue anti-aliasing filter must remove everything above fs/2 before the ADC.

Nyquist frequency

fs/2 = 50 kHz < f = 135 kHz

Nearest multiple of the sampling rate

k = round(135/100) = 1

Alias frequency

fa = |135 − 1·100| = 35 kHz

Answer

fa = 35 kHz

The dashed curve in the figure is the alias: it passes through exactly the same samples.

6.Data acquisition & sampling

Answer: e = 0.1603 %

UART: an asynchronous serial link sends each byte as a frame: one start bit (low), the data bits, an optional parity bit and one or two stop bits (high). The baud rate is the number of bits per second, so one bit lasts Tb = 1/baud and a frame of n bits lasts n/baud. The common 8N1 format has 10 bits per byte. The baud generator divides the clock: baud = fclk/(16·D) with a whole number D, so the real baud rate differs slightly from the target; an error below about 2 % is usually acceptable.

Divider

D = 10·10⁶/(16·2400) = 260.4 → 260

Real baud rate

10·10⁶/(16·260) = 2404 Bd

Error

(2404 − 2400)/2400·100 = 0.1603 %

Answer

e = 0.1603 %

An error below about 2 % is usually acceptable.

ExamProblems · examproblems.com/courses/digital-electronics