Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

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1Formulas and methods

Number systems

Place values: binary 2^k, octal 8^k, hex 16^k
To decimal: Σ d_k·b^k
From decimal: divide by the base, read the remainders bottom-up
Hex ↔ binary: one hex digit = 4 bits
Two’s complement: invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates: A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules: X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan: (X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order: 00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells: loses k variables
4-to-1 multiplexer: F = A′B′I₀ + A′BI₁ + AB′I₂ + ABI₃
Flip-flops: D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters: n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; f_out = f_clk/N
Ripple counter: f_max = 1/(n·t_pd)
Ring and Johnson counters: n and 2n states

Method

For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion: f_s > 2·f_max, f_N = f_s/2
Alias frequency: f_a = |f − k·f_s|, k = round(f/f_s)
Step size: 1 LSB = V_FSR/2ᴺ
Quantisation error (rounding): ±½ LSB
Truncating ADC code: D = ⌊V_in/LSB⌋
Bits for a resolution r: 2ᴺ ≥ span/r
Ideal SQNR, full-scale sine: SQNR = 6.02·N + 1.76 dB
Data rate: channels × f_s × N bit/s
Multiplexed ADC: f_s = 1/(n·(t_c + t_set))
UART: T_b = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider: baud = f_clk/(16·D)

Method

Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
For sampling questions, compare each frequency with f_s/2; a higher frequency appears at f_a = |f − k·f_s| with the nearest multiple of f_s.
For resolution questions, find 1 LSB = V_FSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium

Write −10 as an 8-bit two's complement pattern. Read the pattern as an unsigned binary number: what is its value U in decimal?

N = −108 bit

U =

2.Number systemsHard

Set the bits to the 8-bit result of 0010 1010 XOR 0110 0110. What is the result's value R in decimal?

0010 1010XOR0110 0110

R =

3.Digital logic: gates, K-maps & flip-flopsMedium

Use the Karnaugh map to find the minimal product-of-sums (POS) form of F(A, B, C, D) = Σm(2, 3, 6, 7, 9, 10, 11, 15). How many sum terms (factors) N does it have?

F(A, B, C, D) = Σm(2, 3, 6, 7, 9, 10, 11, 15)

N =

4.Digital logic: gates, K-maps & flip-flopsHard

A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.

Q₀ = 0JK

1clock edge 1
2clock edge 2
3clock edge 3
4clock edge 4
5clock edge 5
6clock edge 6
7clock edge 7
8clock edge 8

5.Data acquisition & samplingMedium

A 12-bit ADC with an input range of 0 to 3.3 V truncates: its output code is ⌊V_in/LSB⌋ with 1 LSB = V_FSR/2ᴺ. Find the decimal output code D for an input of 2.804 V.

N = 12V_FSR = 3.3 VV_in = 2.804 V

D =

6.Data acquisition & samplingHard

A 10-bit ADC streams every sample over a UART at 38400 baud, format 8N1 (start bit, 8 data bits, 1 stop bit). Each sample is sent as 2 whole byte(s) and the link is busy all the time. Find the highest signal frequency f_max that can be sampled without aliasing, in Hz.

baud = 38400 BdN = 108N1

f_max = Hz

3Solutions

1.Number systems

Answer: U = 246

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Invert and add one

10 = 0000 1010

inverted: 1111 0101

+1 → 1111 0110

Read it as unsigned

1111 0110₂ = 256 − 10 = 246

Answer

U = 246

2.Number systems

Answer: R = 76

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Bit by bit

XOR gives 1 where the two bits differ.

0010 1010

XOR 0110 0110

= 0100 1100

Value of the result

0100 1100₂ = 76

Answer

R = 76

3.Digital logic: gates, K-maps & flip-flops

Answer: N = 4

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Group the 0s

Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.

(C + D)

(B′ + C)

(A + C)

(A′ + B′ + D)

Minimal POS form

F = (C + D)(B′ + C)(A + C)(A′ + B′ + D)

N = 4

Answer

N = 4

4.Digital logic: gates, K-maps & flip-flops

Answer: clock edge 3

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at f_clk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Q after every edge

A JK flip-flop: 00 holds, 01 resets (Q = 0), 10 sets (Q = 1), 11 toggles.

1: J = 0, K = 1 → Q = 0

2: J = 1, K = 0 → Q = 1

3: J = 0, K = 1 → Q = 0

4: J = 0, K = 0 → Q = 0

5: J = 1, K = 0 → Q = 1

6: J = 0, K = 0 → Q = 1

7: J = 0, K = 1 → Q = 0

8: J = 1, K = 0 → Q = 1

First change from 1 to 0

clock edge 3

Answer

clock edge 3

5.Data acquisition & sampling

Answer: D = 3480

ADC resolution: an N-bit converter divides its full-scale range V_FSR into 2ᴺ codes, from 0 to 2ᴺ − 1. One step is 1 LSB = V_FSR/2ᴺ: the smallest change the converter can show. A truncating ADC gives the code ⌊V_in/LSB⌋; a rounding ADC is never more than ½ LSB away from the true value, its quantisation error. Every extra bit halves the LSB and adds about 6 dB to the ideal signal-to-quantisation-noise ratio SQNR = 6.02·N + 1.76 dB for a full-scale sine. To reach a resolution r over a span, choose the smallest N with 2ᴺ ≥ span/r.

Step size

1 LSB = 3.3/2¹² = 0.8057 mV

Code

V_in/LSB = 2804/0.8057 = 3480

code = ⌊3480⌋ = 3480

Answer

D = 3480

In binary that is 110110011000.

6.Data acquisition & sampling

Answer: f_max = 960 Hz

UART: an asynchronous serial link sends each byte as a frame: one start bit (low), the data bits, an optional parity bit and one or two stop bits (high). The baud rate is the number of bits per second, so one bit lasts T_b = 1/baud and a frame of n bits lasts n/baud. The common 8N1 format has 10 bits per byte. The baud generator divides the clock: baud = f_clk/(16·D) with a whole number D, so the real baud rate differs slightly from the target; an error below about 2 % is usually acceptable.

Bits per sample on the line

2·10 = 20 bit

Highest sampling rate

f_s,max = 38400/20 = 1920 Hz

Nyquist limit

f_max = 1920/2 = 960 Hz

Answer

f_max = 960 Hz

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