Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

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1Formulas and methods

Number systems

Place values: binary 2^k, octal 8^k, hex 16^k
To decimal: Σ d_k·b^k
From decimal: divide by the base, read the remainders bottom-up
Hex ↔ binary: one hex digit = 4 bits
Two’s complement: invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates: A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules: X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan: (X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order: 00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells: loses k variables
4-to-1 multiplexer: F = A′B′I₀ + A′BI₁ + AB′I₂ + ABI₃
Flip-flops: D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters: n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; f_out = f_clk/N
Ripple counter: f_max = 1/(n·t_pd)
Ring and Johnson counters: n and 2n states

Method

For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion: f_s > 2·f_max, f_N = f_s/2
Alias frequency: f_a = |f − k·f_s|, k = round(f/f_s)
Step size: 1 LSB = V_FSR/2ᴺ
Quantisation error (rounding): ±½ LSB
Truncating ADC code: D = ⌊V_in/LSB⌋
Bits for a resolution r: 2ᴺ ≥ span/r
Ideal SQNR, full-scale sine: SQNR = 6.02·N + 1.76 dB
Data rate: channels × f_s × N bit/s
Multiplexed ADC: f_s = 1/(n·(t_c + t_set))
UART: T_b = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider: baud = f_clk/(16·D)

Method

Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
For sampling questions, compare each frequency with f_s/2; a higher frequency appears at f_a = |f − k·f_s| with the nearest multiple of f_s.
For resolution questions, find 1 LSB = V_FSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium

Set the bits so they store −95 in 8-bit two's complement. Read as an unsigned number, what is the pattern's value U?

N = −958 bit

U =

2.Number systemsHard

Set the bits to the 8-bit result of 1000 0010 OR 1011 1101. What is the result's value R in decimal?

1000 0010OR1011 1101

R =

3.Digital logic: gates, K-maps & flip-flopsMedium

A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = 0, I₁ = 0, I₂ = C′, I₃ = 1. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.

I₀ = 0I₁ = 0I₂ = C′I₃ = 1

N =

4.Digital logic: gates, K-maps & flip-flopsHard

A positive-edge-triggered T flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.

Q₀ = 0T

1clock edge 1
2clock edge 2
3clock edge 3
4clock edge 4
5clock edge 5
6clock edge 6
7clock edge 7

5.Data acquisition & samplingMedium

A UART sends bytes at 9600 baud in the format 8E2: 8 data bits, an even parity bit and 2 stop bit(s), plus the start bit. Find the largest number of data bytes per second it can transfer.

baud = 9600 Bd8E2

R_B = B/s

6.Data acquisition & samplingHard

An audio measurement needs an ideal signal-to-quantisation-noise ratio of at least 40 dB for a full-scale sine wave. Find the smallest number of ADC bits N.

SQNR ≥ 40 dB

N =

3Solutions

1.Number systems

Answer: U = 161

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Invert and add one

95 = 0101 1111

inverted: 1010 0000

+1 → 1010 0001

Read it as unsigned

1010 0001₂ = 256 − 95 = 161

Answer

U = 161

2.Number systems

Answer: R = 191

Bit by bit

OR gives 1 where at least one bit is 1.

1000 0010

OR 1011 1101

= 1011 1111

Value of the result

1011 1111₂ = 191

Answer

R = 191

3.Digital logic: gates, K-maps & flip-flops

Answer: N = 3

Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.

Output expression

F = AB′C′ + AB

Rows with F = 1

ABC = 100, 110, 111

N = 3

Answer

N = 3

4.Digital logic: gates, K-maps & flip-flops

Answer: clock edge 6

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at f_clk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Q after every edge

A T flip-flop toggles at each rising edge with T = 1 and holds with T = 0.

1: T = 0 → Q = 0

2: T = 0 → Q = 0

3: T = 0 → Q = 0

4: T = 0 → Q = 0

5: T = 1 → Q = 1

6: T = 1 → Q = 0

7: T = 0 → Q = 0

First change from 1 to 0

clock edge 6

Answer

clock edge 6

5.Data acquisition & sampling

Answer: R_B = 800 B/s

UART: an asynchronous serial link sends each byte as a frame: one start bit (low), the data bits, an optional parity bit and one or two stop bits (high). The baud rate is the number of bits per second, so one bit lasts T_b = 1/baud and a frame of n bits lasts n/baud. The common 8N1 format has 10 bits per byte. The baud generator divides the clock: baud = f_clk/(16·D) with a whole number D, so the real baud rate differs slightly from the target; an error below about 2 % is usually acceptable.

Bits per frame

1 + 8 + 1 + 2 = 12

Byte rate

9600/12 = 800 B/s

Answer

R_B = 800 B/s

6.Data acquisition & sampling

Answer: N = 7

ADC resolution: an N-bit converter divides its full-scale range V_FSR into 2ᴺ codes, from 0 to 2ᴺ − 1. One step is 1 LSB = V_FSR/2ᴺ: the smallest change the converter can show. A truncating ADC gives the code ⌊V_in/LSB⌋; a rounding ADC is never more than ½ LSB away from the true value, its quantisation error. Every extra bit halves the LSB and adds about 6 dB to the ideal signal-to-quantisation-noise ratio SQNR = 6.02·N + 1.76 dB for a full-scale sine. To reach a resolution r over a span, choose the smallest N with 2ᴺ ≥ span/r.

Solve for N

N ≥ (40 − 1.76)/6.02 = 6.352

Round up

N = 7

check: 6.02·7 + 1.76 = 43.9 dB ≥ 40 dB

Answer

N = 7

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