Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

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1Formulas and methods

Number systems

Place values
binary 2k, octal 8k, hex 16k
To decimal
Σ dk·bk
From decimal
divide by the base, read the remainders bottom-up
Hex ↔ binary
one hex digit = 4 bits
Two’s complement
invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion
fs > 2·fmax, fN = fs/2
Alias frequency
fa = |f − k·fs|, k = round(f/fs)
Step size
1 LSB = VFSR/2ᴺ
Quantisation error (rounding)
±½ LSB
Truncating ADC code
D = ⌊Vin/LSB⌋
Bits for a resolution r
2ᴺ ≥ span/r
Ideal SQNR, full-scale sine
SQNR = 6.02·N + 1.76 dB
Data rate
channels × fs × N bit/s
Multiplexed ADC
fs = 1/(n·(tc + tset))
UART
Tb = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider
baud = fclk/(16·D)

Method

  1. Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
  2. For sampling questions, compare each frequency with fs/2; a higher frequency appears at fa = |f − k·fs| with the nearest multiple of fs.
  3. For resolution questions, find 1 LSB = VFSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
  4. For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium
place values in two's complement1−12816403211608041211

The 8-bit pattern 1101 0011 stores a signed integer in two's complement. What is its value N in decimal?

1101 00118 bit
N =
2.Number systemsHard
10 bits, unsigned, N = ???????????

What is the largest unsigned integer N that fits in 10 bits?

10 bit
N =
3.Digital logic: gates, K-maps & flip-flopsMedium
ABCD000111100001111010110302041517061121130151140819011110

Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C, D) = Σm(0, 1, 5, 7, 9, 10, 12, 13, 14). How many product terms N does it have?

F(A, B, C, D) = Σm(0, 1, 5, 7, 9, 10, 12, 13, 14)
N =
4.Digital logic: gates, K-maps & flip-flopsHard
CLKJK12345678

A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.

Q₀ = 0JK
  1. 1clock edge 1
  2. 2clock edge 2
  3. 3clock edge 3
  4. 4clock edge 4
  5. 5clock edge 5
  6. 6clock edge 6
  7. 7clock edge 7
  8. 8clock edge 8
5.Data acquisition & samplingMedium
128⋮8 ch∿01N = 1625 kHz? MB

A recorder samples 8 channels at 25 kHz each with a 16-bit ADC. Each sample is stored in whole bytes. Find the memory M needed for a 5 min recording, in MB (1 MB = 10⁶ bytes).

n = 8fs = 25 kHzN = 16t = 5 min
M = MB
6.Data acquisition & samplingHard
126⋮6 ch∿01tc​ = 20 µstset​ = 5 µsfs​ = ?

A 6-channel multiplexer feeds one ADC. Each conversion takes 20 µs, and after every channel switch the input needs 5 µs to settle. The channels are scanned in turn without pause. Find the sampling rate fs of each channel, in kHz.

n = 6tc = 20 µstset = 5 µs
fs = kHz

3Solutions

1.Number systems

Answer: N = −45

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Add the place values

The other bits keep their normal positive values.

−128 + 64 + 16 + 2 + 1 = −45

Answer

N = −45
2.Number systems

Answer: N = 1023

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Largest value

210 − 1 = 1023

Answer

N = 1023
3.Digital logic: gates, K-maps & flip-flops

Answer: N = 5

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

ABCD000111100001111010110302041517061121130151140819011110

Group the 1s

Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.

C′D
ACD′
A′BD
ABD′
A′B′C′

Minimal SOP form

F = C′D + ACD′ + A′BD + ABD′ + A′B′C′
N = 5

Answer

N = 5

Another grouping of the same size exists; it has the same number of terms and literals.

4.Digital logic: gates, K-maps & flip-flops

Answer: clock edge 5

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Q after every edge

A JK flip-flop: 00 holds, 01 resets (Q = 0), 10 sets (Q = 1), 11 toggles.

1: J = 0, K = 1 → Q = 0
2: J = 0, K = 0 → Q = 0
3: J = 1, K = 0 → Q = 1
4: J = 0, K = 0 → Q = 1
5: J = 0, K = 1 → Q = 0
6: J = 1, K = 0 → Q = 1
7: J = 1, K = 0 → Q = 1
8: J = 0, K = 1 → Q = 0

First change from 1 to 0

clock edge 5

Answer

clock edge 5
5.Data acquisition & sampling

Answer: M = 120 MB

Data rates: every channel delivers fs samples per second of N bits, so the raw rate is channels × fs × N bit/s. In memory a sample takes whole bytes (a 12-bit sample is stored in 2 bytes), so the memory for a recording is channels × fs × bytes per sample × time. A multiplexed ADC converts the channels one after another: each conversion (with settling) takes t, so one round of n channels takes n·t and each channel is sampled at 1/(n·t).

Bytes per sample

⌈16/8⌉ = 2 B

Byte rate

8·25000·2 = 400000 B/s

Memory

M = 400000·300 = 1.2 × 10⁸ B = 120 MB

Answer

M = 120 MB
6.Data acquisition & sampling

Answer: fs = 6.667 kHz

Data rates: every channel delivers fs samples per second of N bits, so the raw rate is channels × fs × N bit/s. In memory a sample takes whole bytes (a 12-bit sample is stored in 2 bytes), so the memory for a recording is channels × fs × bytes per sample × time. A multiplexed ADC converts the channels one after another: each conversion (with settling) takes t, so one round of n channels takes n·t and each channel is sampled at 1/(n·t).

Time per channel

20 + 5 = 25 µs

Time per scan

6·25 = 150 µs

Sampling rate per channel

fs = 1/150 µs = 6.667 kHz

Answer

fs = 6.667 kHz

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