Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

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1Formulas and methods

Number systems

Place values
binary 2k, octal 8k, hex 16k
To decimal
Σ dk·bk
From decimal
divide by the base, read the remainders bottom-up
Hex ↔ binary
one hex digit = 4 bits
Two’s complement
invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion
fs > 2·fmax, fN = fs/2
Alias frequency
fa = |f − k·fs|, k = round(f/fs)
Step size
1 LSB = VFSR/2ᴺ
Quantisation error (rounding)
±½ LSB
Truncating ADC code
D = ⌊Vin/LSB⌋
Bits for a resolution r
2ᴺ ≥ span/r
Ideal SQNR, full-scale sine
SQNR = 6.02·N + 1.76 dB
Data rate
channels × fs × N bit/s
Multiplexed ADC
fs = 1/(n·(tc + tset))
UART
Tb = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider
baud = fclk/(16·D)

Method

  1. Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
  2. For sampling questions, compare each frequency with fs/2; a higher frequency appears at fa = |f − k·fs| with the nearest multiple of fs.
  3. For resolution questions, find 1 LSB = VFSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
  4. For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium
place values in two's complement1−12806403211608041211

The 8-bit pattern 1001 0011 stores a signed integer in two's complement. What is its value N in decimal?

1001 00118 bit
N =
2.Number systemsHard
10 bits, unsigned, N = ???????????

What is the largest unsigned integer N that fits in 10 bits?

10 bit
N =
3.Digital logic: gates, K-maps & flip-flopsMedium
ABCD000111100001111010011312141507061120130151141809011110

Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C, D) = Σm(0, 2, 3, 4, 5, 8, 10, 12, 14). How many literals L does it contain in total (a primed variable counts as one literal)?

F(A, B, C, D) = Σm(0, 2, 3, 4, 5, 8, 10, 12, 14)
L =
4.Digital logic: gates, K-maps & flip-flopsHard
TQ0​Q0​TQ1​Q1​TQ2​Q2​TQ3​Q3​CLKMOD-10

A synchronous decade (mod-10) counter counts 0, 1, …, 9 and then returns to 0. It starts at 8. Which count Q (in decimal) does it show after 14 clock pulses?

Q0 = 814N = 10
Q =
5.Data acquisition & samplingMedium
SD0​D1​D2​D3​D4​D5​D6​D7​Tb​10·Tb​4800 Bd, 8N1

A UART sends bytes at 4800 baud in the format 8N1: 8 data bits, no parity and 1 stop bit(s), plus the start bit. Find the largest number of data bytes per second it can transfer.

baud = 4800 Bd8N1
RB = B/s
6.Data acquisition & samplingHard
1216⋮16 ch∿01tc​ = 8 µstset​ = 5 µsfs​ = ?

A 16-channel multiplexer feeds one ADC. Each conversion takes 8 µs, and after every channel switch the input needs 5 µs to settle. The channels are scanned in turn without pause. Find the sampling rate fs of each channel, in kHz.

n = 16tc = 8 µstset = 5 µs
fs = kHz

3Solutions

1.Number systems

Answer: N = −109

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Add the place values

The other bits keep their normal positive values.

−128 + 16 + 2 + 1 = −109

Answer

N = −109
2.Number systems

Answer: N = 1023

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Largest value

210 − 1 = 1023

Answer

N = 1023
3.Digital logic: gates, K-maps & flip-flops

Answer: L = 10

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

ABCD000111100001111010011312141507061120130151141809011110

Group the 1s

Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.

C′D′
AD′
A′B′C
A′BC′

Minimal SOP form

F = C′D′ + AD′ + A′B′C + A′BC′
L = 10

Answer

L = 10

Another grouping of the same size exists; it has the same number of terms and literals.

4.Digital logic: gates, K-maps & flip-flops

Answer: Q = 2

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Full cycles

Every 10 pulses bring the counter back to the same state.

14 = 1·10 + 4

Count after the remaining pulses

Q = (8 + 4) mod 10 = 2
Q = 0010₂

Answer

Q = 2
5.Data acquisition & sampling

Answer: RB = 480 B/s

UART: an asynchronous serial link sends each byte as a frame: one start bit (low), the data bits, an optional parity bit and one or two stop bits (high). The baud rate is the number of bits per second, so one bit lasts Tb = 1/baud and a frame of n bits lasts n/baud. The common 8N1 format has 10 bits per byte. The baud generator divides the clock: baud = fclk/(16·D) with a whole number D, so the real baud rate differs slightly from the target; an error below about 2 % is usually acceptable.

Bits per frame

1 + 8 + 0 + 1 = 10

Byte rate

4800/10 = 480 B/s

Answer

RB = 480 B/s
6.Data acquisition & sampling

Answer: fs = 4.808 kHz

Data rates: every channel delivers fs samples per second of N bits, so the raw rate is channels × fs × N bit/s. In memory a sample takes whole bytes (a 12-bit sample is stored in 2 bytes), so the memory for a recording is channels × fs × bytes per sample × time. A multiplexed ADC converts the channels one after another: each conversion (with settling) takes t, so one round of n channels takes n·t and each channel is sampled at 1/(n·t).

Time per channel

8 + 5 = 13 µs

Time per scan

16·13 = 208 µs

Sampling rate per channel

fs = 1/208 µs = 4.808 kHz

Answer

fs = 4.808 kHz

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