Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

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1Formulas and methods

Number systems

Place values
binary 2k, octal 8k, hex 16k
To decimal
Σ dk·bk
From decimal
divide by the base, read the remainders bottom-up
Hex ↔ binary
one hex digit = 4 bits
Two’s complement
invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion
fs > 2·fmax, fN = fs/2
Alias frequency
fa = |f − k·fs|, k = round(f/fs)
Step size
1 LSB = VFSR/2ᴺ
Quantisation error (rounding)
±½ LSB
Truncating ADC code
D = ⌊Vin/LSB⌋
Bits for a resolution r
2ᴺ ≥ span/r
Ideal SQNR, full-scale sine
SQNR = 6.02·N + 1.76 dB
Data rate
channels × fs × N bit/s
Multiplexed ADC
fs = 1/(n·(tc + tset))
UART
Tb = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider
baud = fclk/(16·D)

Method

  1. Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
  2. For sampling questions, compare each frequency with fs/2; a higher frequency appears at fa = |f − k·fs| with the nearest multiple of fs.
  3. For resolution questions, find 1 LSB = VFSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
  4. For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium
place values in two's complement1−12806413201618141211

The 8-bit pattern 1010 1111 stores a signed integer in two's complement. What is its value N in decimal?

1010 11118 bit
N =
2.Number systemsHard
click the bits to set them012806403201608040201

Set the bits to the 8-bit result of 0111 1100 >> 1. What is the result's value R in decimal?

0111 1100>> 1
R =
3.Digital logic: gates, K-maps & flip-flopsMedium
ABCD000111100001111000010312141507061121130151141819011110

Use the Karnaugh map to find the minimal product-of-sums (POS) form of F(A, B, C, D) = Σm(2, 4, 5, 8, 9, 10, 12, 13, 14). How many sum terms (factors) N does it have?

F(A, B, C, D) = Σm(2, 4, 5, 8, 9, 10, 12, 13, 14)
N =
4.Digital logic: gates, K-maps & flip-flopsHard
TQ0​Q0​TQ1​Q1​TQ2​Q2​TQ3​Q3​CLK

A 4-bit ripple (asynchronous) counter is built from flip-flops with a propagation delay of 8 ns each. All outputs must have settled before the next clock edge. Find the maximum clock frequency fmax.

n = 4tpd = 8 ns
fmax = MHz
5.Data acquisition & samplingMedium
tTs​ = 1/fs​f = 14.8 kHzfs​ = 8 kHz

A 14.8 kHz sine wave is sampled at 8 kHz without an anti-aliasing filter. At which frequency fa does it appear in the samples? Give it in Hz.

f = 14.8 kHzfs = 8 kHz
fa = Hz
6.Data acquisition & samplingHard
T10 mV/°C×20∿01N = 12, 3.3 V? °C/LSB

A temperature sensor gives 10 mV/°C (0 V at 0 °C). Its signal is amplified 20 times and fed to a 12-bit ADC with a range of 0 to 3.3 V (1 LSB = VFSR/2ᴺ). Find the temperature change ΔTLSB that corresponds to one LSB.

S = 10 mV/°CG = 20N = 12VFSR = 3.3 V
ΔTLSB = °C

3Solutions

1.Number systems

Answer: N = −81

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Add the place values

The other bits keep their normal positive values.

−128 + 32 + 8 + 4 + 2 + 1 = −81

Answer

N = −81
2.Number systems

Answer: R = 62

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Bit by bit

Shifting right by 1 moves every bit 1 places to the right; bits that fall off the right end are lost and zeros come in on the left.

0111 1100 >> 1
= 0011 1110

Value of the result

0011 1110₂ = 62

Answer

R = 62
3.Digital logic: gates, K-maps & flip-flops

Answer: N = 3

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

ABCD000111100001111000010312141507061121130151141819011110

Group the 0s

Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.

(C′ + D′)
(A + B + C)
(A + B′ + C′)

Minimal POS form

F = (C′ + D′)(A + B + C)(A + B′ + C′)
N = 3

Answer

N = 3
4.Digital logic: gates, K-maps & flip-flops

Answer: fmax = 31.25 MHz

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Worst-case settling time

T = 4·8 ns = 32 ns

Maximum frequency

fmax = 1/32 ns = 31.25 MHz

Answer

fmax = 31.25 MHz
5.Data acquisition & sampling

Answer: fa = 1200 Hz

Sampling: an ADC measures the signal fs times per second. By the Nyquist–Shannon theorem a frequency f is captured correctly only while f < fs/2, the Nyquist (folding) frequency, so the sampling rate must exceed twice the highest signal frequency. A higher frequency is not lost: it shows up as an alias at fa = |f − k·fs|, with the whole number k that brings the result between 0 and fs/2. The samples cannot tell the two apart, so an analogue anti-aliasing filter must remove everything above fs/2 before the ADC.

Nyquist frequency

fs/2 = 4 kHz < f = 14.8 kHz

Nearest multiple of the sampling rate

k = round(14800/8000) = 2

Alias frequency

fa = |14800 − 2·8000| = 1200 Hz

Answer

fa = 1200 Hz

The dashed curve in the figure is the alias: it passes through exactly the same samples.

6.Data acquisition & sampling

Answer: ΔTLSB = 0.004028 °C

ADC resolution: an N-bit converter divides its full-scale range VFSR into 2ᴺ codes, from 0 to 2ᴺ − 1. One step is 1 LSB = VFSR/2ᴺ: the smallest change the converter can show. A truncating ADC gives the code ⌊Vin/LSB⌋; a rounding ADC is never more than ½ LSB away from the true value, its quantisation error. Every extra bit halves the LSB and adds about 6 dB to the ideal signal-to-quantisation-noise ratio SQNR = 6.02·N + 1.76 dB for a full-scale sine. To reach a resolution r over a span, choose the smallest N with 2ᴺ ≥ span/r.

Step size

1 LSB = 3300/4096 = 0.8057 mV

Sensitivity at the ADC

10·20 = 200 mV/°C

Temperature resolution

ΔTLSB = 0.8057/200 = 0.004028 °C

Answer

ΔTLSB = 0.004028 °C

The ADC reaches full scale at 16.5 °C.

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