Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

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1Formulas and methods

Number systems

Place values
binary 2k, octal 8k, hex 16k
To decimal
Σ dk·bk
From decimal
divide by the base, read the remainders bottom-up
Hex ↔ binary
one hex digit = 4 bits
Two’s complement
invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion
fs > 2·fmax, fN = fs/2
Alias frequency
fa = |f − k·fs|, k = round(f/fs)
Step size
1 LSB = VFSR/2ᴺ
Quantisation error (rounding)
±½ LSB
Truncating ADC code
D = ⌊Vin/LSB⌋
Bits for a resolution r
2ᴺ ≥ span/r
Ideal SQNR, full-scale sine
SQNR = 6.02·N + 1.76 dB
Data rate
channels × fs × N bit/s
Multiplexed ADC
fs = 1/(n·(tc + tset))
UART
Tb = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider
baud = fclk/(16·D)

Method

  1. Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
  2. For sampling questions, compare each frequency with fs/2; a higher frequency appears at fa = |f − k·fs| with the nearest multiple of fs.
  3. For resolution questions, find 1 LSB = VFSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
  4. For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium
8-bit two's complement?−128?64?32?16?8?4?2?1

Write −12 as an 8-bit two's complement pattern. Read the pattern as an unsigned binary number: what is its value U in decimal?

N = −128 bit
U =
2.Number systemsHard
4255 codes, b = ? bits?2ᵇ⁻¹…?4?2?1

A system must give every one of 4255 items its own binary code of the same length. What is the smallest number of bits b needed?

4255
b = bit
3.Digital logic: gates, K-maps & flip-flopsMedium
ABC00011110011011031214051716

Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C) = Σm(0, 1, 2, 4, 6, 7). How many product terms N does it have?

F(A, B, C) = Σm(0, 1, 2, 4, 6, 7)
N =
4.Digital logic: gates, K-maps & flip-flopsHard
DQ3​Q3​DQ2​Q2​DQ1​Q1​DQ0​Q0​CLKSHIFT

A 4-bit shift register Q₃Q₂Q₁Q₀ holds 1000. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀, Q₀ is lost) and the serial input enters Q₃. The serial input is 0, 0, 1, 1 at the 4 edges. Give the final state Q = Q₃Q₂Q₁Q₀ as a decimal number.

Q₃Q₂Q₁Q₀ = 10000, 0, 1, 1
Q =
5.Data acquisition & samplingMedium
tTs​ = 1/fs​f = 850 Hzfs​ = 1 kHz

An 850 Hz sine wave is sampled at 1 kHz without an anti-aliasing filter. At which frequency fa does it appear in the samples? Give it in Hz.

f = 850 Hzfs = 1 kHz
fa = Hz
6.Data acquisition & samplingHard
Vin​N = ?VFSR​2ᴺ − 101 LSB

An audio measurement needs an ideal signal-to-quantisation-noise ratio of at least 70 dB for a full-scale sine wave. Find the smallest number of ADC bits N.

SQNR ≥ 70 dB
N =

3Solutions

1.Number systems

Answer: U = 244

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Invert and add one

12 = 0000 1100
inverted: 1111 0011
+1 → 1111 0100

Read it as unsigned

1111 0100₂ = 256 − 12 = 244

Answer

U = 244
2.Number systems

Answer: b = 13 bit

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Powers of two

212 = 4096 < 4255
213 = 8192 ≥ 4255

Answer

b = 13
3.Digital logic: gates, K-maps & flip-flops

Answer: N = 3

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

ABC00011110011011031214051716

Group the 1s

Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.

C′
A′B′
AB

Minimal SOP form

F = C′ + A′B′ + AB
N = 3

Answer

N = 3
4.Digital logic: gates, K-maps & flip-flops

Answer: Q = 12

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

State after every edge

1000 → 0100 → 0010 → 1001 → 1100

Decimal value

1100₂ = 12

Answer

Q = 12
5.Data acquisition & sampling

Answer: fa = 150 Hz

Sampling: an ADC measures the signal fs times per second. By the Nyquist–Shannon theorem a frequency f is captured correctly only while f < fs/2, the Nyquist (folding) frequency, so the sampling rate must exceed twice the highest signal frequency. A higher frequency is not lost: it shows up as an alias at fa = |f − k·fs|, with the whole number k that brings the result between 0 and fs/2. The samples cannot tell the two apart, so an analogue anti-aliasing filter must remove everything above fs/2 before the ADC.

Nyquist frequency

fs/2 = 500 Hz < f = 850 Hz

Nearest multiple of the sampling rate

k = round(850/1000) = 1

Alias frequency

fa = |850 − 1·1000| = 150 Hz

Answer

fa = 150 Hz

The dashed curve in the figure is the alias: it passes through exactly the same samples.

6.Data acquisition & sampling

Answer: N = 12

ADC resolution: an N-bit converter divides its full-scale range VFSR into 2ᴺ codes, from 0 to 2ᴺ − 1. One step is 1 LSB = VFSR/2ᴺ: the smallest change the converter can show. A truncating ADC gives the code ⌊Vin/LSB⌋; a rounding ADC is never more than ½ LSB away from the true value, its quantisation error. Every extra bit halves the LSB and adds about 6 dB to the ideal signal-to-quantisation-noise ratio SQNR = 6.02·N + 1.76 dB for a full-scale sine. To reach a resolution r over a span, choose the smallest N with 2ᴺ ≥ span/r.

Solve for N

N ≥ (70 − 1.76)/6.02 = 11.34

Round up

N = 12
check: 6.02·12 + 1.76 = 74 dB ≥ 70 dB

Answer

N = 12

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