Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

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1Formulas and methods

Diodes & transistors

Diode (constant drop)
VD = 0.7 V when conducting
Active region
VBE = 0.7 V, IC = β·IB, IE = (β + 1)·IB
Fixed bias
IB = (VCC − 0.7)/RB
Divider bias
IB = (VTH − 0.7)/(RTH + (β + 1)RE)
Thévenin of the divider
VTH = VCC·R2/(R1 + R2), RTH = R1∥R2
Collector loop
VCE = VCC − ICRC − IERE
Saturation
IC(sat) = (VCC − VCE(sat))/RC, IB ≥ IC(sat)/β

Op-amp circuits

Inverting amplifier
Vout = −(Rf/Rin)·Vin
Non-inverting amplifier
Vout = (1 + Rf/R1)·Vin
Summing amplifier
Vout = −Rf(V1/R1 + V2/R2)
Ideal op-amp
V+ = V−, Iin = 0

RC & RL transients

Time constant
τ = RC | τ = L/R
Response
x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ
Capacitor at DC
open circuit; vC cannot jump
Inductor at DC
short circuit; iL cannot jump
Settled
t ≈ 5τ

Method

  1. Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
  2. Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
  3. Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
  4. Use x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ.

Series & parallel resistors

Resistors in series
Req = R1 + R2 + …
Resistors in parallel
1/Req = 1/R1 + 1/R2 + …
Two in parallel
Req = R1R2 / (R1 + R2)
Ohm's law
V = I·R
Power
P = V·I = I²R = V²/R

Method

  1. Start at the end of the network furthest from the terminals.
  2. Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
  3. Redraw the circuit after each step.
  4. Repeat until one resistor is left between the terminals.

DC-DC converters

Buck
Vo = D·Vin
Boost
Vo = Vin/(1 − D)
Inverting buck-boost
|Vo| = Vin·D/(1 − D)
Ideal power balance
VinIin = VoIo
Inductor ripple
ΔIL = VL,on·D/(L·f); buck Vin − Vo, boost and buck-boost Vin
Average inductor current
buck Io; boost and buck-boost Io/(1 − D)
Output ripple
buck ΔIL/(8fC); boost and buck-boost Io·D/(fC)
CCM boundary
buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

  1. Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
  2. Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
  3. Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
  4. For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.

Wheatstone bridge & strain gauges

Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε

Method

  1. Treat the bridge as two voltage dividers across the same supply.
  2. For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
  3. For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
  4. For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium
RC​ = 2.7 kΩβ = 80RE​ = 1.2 kΩVCC​ = 20 VR1​ = 39 kΩR2​ = 10 kΩ

An NPN transistor with β = 80 has voltage-divider bias from VCC = 20 V: R₁ = 39 kΩ from VCC to the base and R₂ = 10 kΩ from the base to ground. The collector resistor is RC = 2.7 kΩ and the emitter resistor is RE = 1.2 kΩ. Take VBE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector–emitter voltage VCE.

VCC = 20 VR1 = 39 kΩR2 = 10 kΩRC = 2.7 kΩRE = 1.2 kΩβ = 80
VCE = V
2.Diodes & transistorsHard
RC​ = 1 kΩβ = 150VCC​ = 24 V5 VRB​ = ?

An NPN transistor with β = 150 switches a 1 kΩ load resistor connected between VCC = 24 V and its collector. The emitter is grounded. The base is driven from a 5 V logic output through a base resistor RB. Take VBE = 0.7 V and VCE(sat) = 0.2 V. For reliable switching, design for a base current 10 times the minimum needed for saturation. Find RB in kΩ.

VCC = 24 VRC = 1 kΩβ = 150Vin = 5 VVBE = 0.7 VVCE(sat) = 0.2 Voverdrive = 10
RB = kΩ
3.Op-amp circuitsMedium
−+Vout​Rf​ = ?R1​ = 22 kΩVin​

Choose the feedback resistor Rf that gives this non-inverting amplifier a voltage gain of 5.

R1 = 22 kΩAv = 5
Rf = kΩ
4.Op-amp circuitsHard
−+Vout​Rf​ = 22 kΩV1​ = 1.2 VR1​ = 4.7 kΩV2​ = 0.3 VR2​ = 100 kΩ

The summing amplifier uses an ideal op-amp with ±15 V supplies. Find the output voltage Vout.

V1 = 1.2 VV2 = 0.3 VR1 = 4.7 kΩR2 = 100 kΩRf = 22 kΩ
Vout = V
5.RC & RL transientsMedium
+−Vs​24 Vt = 0R1​ = 10 kΩR2​ = 3.3 kΩC22 µF+−vC​

The source Vₛ charges the capacitor through R₁, and R₂ is connected in parallel with C. The capacitor is uncharged when the switch closes at t = 0. Find the capacitor voltage vC at t = 25 ms.

Vs = 24 VR1 = 10 kΩR2 = 3.3 kΩC = 22 µFt = 25 ms
vC = V
6.RC & RL transientsHard
+−Vs​5 Vt = 0R = ?C100 µF+−vC​

A timer starts charging an uncharged capacitor through a resistor from a 5 V supply at t = 0. It must trigger when the capacitor voltage reaches 3.16 V, exactly 50 ms after the start. With C = 100 µF, find the resistance R needed.

Vs = 5 VVth = 3.16 VT = 50 msC = 100 µF
R = kΩ
7.Series & parallel resistorsMedium
R1​ = 2 ΩIR1​R3​ = 8 Ω+−V1​12 VR2​4 ΩAR4​3 ΩB

Find the current IR1 delivered by the source, which flows through R1.

V1 = 12 VR1 = 2 ΩR2 = 4 ΩR3 = 8 ΩR4 = 3 Ω
IR1 = A
8.Series & parallel resistorsHard
R1​ = 6 ΩR3​ = 2 ΩR5​ = 4 Ω+−V1​24 VR2​8 ΩAR4​6 ΩBR6​8 Ω

Find the equivalent resistance Req seen by the source V1.

V1 = 24 VR1 = 6 ΩR2 = 8 ΩR3 = 2 ΩR4 = 6 ΩR5 = 4 ΩR6 = 8 Ω
Req = Ω
9.DC-DC convertersMedium
tiL​Imax​Imin​ΔI = ?DTT2T

An ideal inverting buck-boost converter turns 9 V into −27 V at 20 kHz with L = 330 µH. Find the peak-to-peak inductor ripple current ΔIL.

Vin​ = 9 VVo​ = −27 Vf = 20 kHzL = 330 µH
ΔIL = A
10.DC-DC convertersHard
tiL​Imax​IL​DTT2T

An ideal buck converter turns 36 V into 27 V for an 8 Ω load at 40 kHz. Find the smallest inductance Lcrit for continuous conduction.

Vin​ = 36 VVo​ = 27 Vf = 40 kHzR = 8 Ω
Lcrit = µH
11.Wheatstone bridge & strain gaugesMedium
+−9 V200 Ω200 Ω + ΔR200 Ω200 Ωab+−Vab​ = ?

A bridge has four 200 Ω arms and Vs = 9 V. The sensor R₂ increases by ΔR = 50 Ω. Find the exact output Vab in mV.

Vs = 9 VR = 200 ΩΔR = 50 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
+−3 V120 Ω120 Ω + ΔR120 Ω120 Ωab+−Vo​ = ?

A bridge with 120 Ω arms is excited with 3 V and has one active gauge (quarter bridge). The gauge factor is 2 and the strain is 250 µε. Find the bridge output Vo in mV.

Vs = 3 VGF = 2ε = 250 µε
Vo = mV
13.Digital logic: gates, K-maps & flip-flopsMedium
ABC000111100101324576

Simplify F = AC′ + BC + ABC′ to its minimal sum-of-products form. How many literals L does the simplified expression contain?

F = AC′ + BC + ABC′
L =
14.Digital logic: gates, K-maps & flip-flopsHard
TQ0​Q0​TQ1​Q1​TQ2​Q2​TQ3​Q3​CLKUP

A 4-bit binary up counter starts at 15 (decimal, Q = 1111). Which count Q (in decimal) does it show after 43 clock pulses?

Q0 = 1543n = 4
Q =

3Solutions

1.Diodes & transistors

Answer: VCE = 9.928 V

BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.

Thévenin equivalent of the divider

VTH = 20·10/(39 + 10) = 4.082 V
RTH = 39·10/(39 + 10) = 7.959 kΩ

Base current

KVL around the base loop; the emitter current is (β + 1)·IB.

IB = (4.082 − 0.7)/(7.959 + 81·1.2) = 32.16 µA

Collector current

IC = 80·32.16 µA = 2.573 mA
IE = 81·32.16 µA = 2.605 mA

Collector–emitter voltage

VCE = 20 − 2.573·2.7 − 2.605·1.2 = 9.928 V

Answer

VCE = 9.928 V
2.Diodes & transistors

Answer: RB = 2.71 kΩ

BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.

Collector current in saturation

IC(sat) = (24 − 0.2)/1000 = 23.8 mA

Minimum base current

IB(min) = IC(sat)/β = 23.8/150 = 158.7 µA

Design base current

IB = 10·158.7 µA = 1587 µA

Base resistor

RB = (5 − 0.7)/IB = 4.3 V/1.587 mA = 2.71 kΩ

Answer

RB = 2.71 kΩ
3.Op-amp circuits

Answer: Rf = 88 kΩ

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Gain of a non-inverting amplifier

V₋ = V₊ = Vin, and the current through R₁ also flows through Rf, so Vout = Vin·(1 + Rf/R₁).

Av = 1 + Rf/R1
Rf = (5 − 1)·22 = 88 kΩ

Answer

Rf = 88 kΩ
4.Op-amp circuits

Answer: Vout = −5.683 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Input currents

V₋ = 0, so each input resistor has its full input voltage across it.

I1 = V1/R1 = 1.2/4.7 = 0.2553 mA
I2 = V2/R2 = 0.3/100 = 0.003 mA
If = I1 + I2 = 0.2583 mA

Output voltage

Vout = −Rf·If = −22·0.2583 = −5.683 V

Answer

Vout = −5.683 V
5.RC & RL transients

Answer: vC = 2.188 V

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Thévenin equivalent seen by the capacitor

Short the source to find Rth; open the capacitor to find the voltage it will settle at.

Rth = R1 ∥ R2 = 10·3.3/(10 + 3.3) = 2.481 kΩ
vC(∞) = 24·3.3/(10 + 3.3) = 5.955 V

Time constant

τ = Rth·C = 2.481·22 = 54.59 ms

Charging curve

vC(t) = 5.955·(1 − e−25/54.59) = 2.188 V

Answer

vC = 2.188 V
6.RC & RL transients

Answer: R = 0.5002 kΩ

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Required time constant

3.16 = 5·(1 − e−50/τ) → τ = 50/ln(5/(5 − 3.16))
τ = 50/0.9997 = 50.02 ms

Resistance

kΩ times µF gives milliseconds.

R = τ/C = 50.02/100 = 0.5002 kΩ

Answer

R = 0.5002 kΩ
7.Series & parallel resistors

Answer: IR1 = 2.432 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 2 ΩR3​ = 8 Ω+−V1​12 VR2​4 ΩAR4​3 ΩB

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R3 + R4 = 8 + 3 = 11 Ω
R2 ∥ 11 = 4·11/(4+11) = 2.933 Ω
Req = R1 + 2.933 = 2 + 2.933 = 4.933 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 12/4.933 = 2.432 A

Answer

IR1 = 2.432 A
8.Series & parallel resistors

Answer: Req = 9.429 Ω

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 6 ΩR3​ = 2 ΩR5​ = 4 Ω+−V1​24 VR2​8 ΩAR4​6 ΩBR6​8 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R5 + R6 = 4 + 8 = 12 Ω
R4 ∥ 12 = 4 Ω
R3 + 4 = 6 Ω
R2 ∥ 6 = 3.429 Ω
Req = R1 + 3.429 = 6 + 3.429 = 9.429 Ω

Answer

Req = 9.429 Ω
9.DC-DC converters

Answer: ΔIL = 1.023 A

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 27/(9 + 27) = 0.75

Inductor voltage during the on-time

While S is on, the inductor sits directly across Vin.

VL = 9 V

Ripple current

ΔIL = VL·D/(L·f) = 9·0.75/(330·10⁻⁶·20·10³) = 1.023 A

Answer

ΔIL = 1.023 A
10.DC-DC converters

Answer: Lcrit = 25 µH

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 27/36 = 0.75

Boundary condition

Set the average inductor current equal to half the ripple current and solve for L.

Lcrit = (1 − D)·R/(2f)

Critical inductance

Lcrit = (1 − 0.75)·8/(240·10³) = 25 µH

Answer

Lcrit = 25 µH
11.Wheatstone bridge & strain gauges

Answer: Vab = 500 mV

Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.

Node voltages

Va = 9·250/450 = 5 V
Vb = 4.5 V

Output

Vab = 500 mV

Answer

Vab = 500 mV

The linear estimate Vs·ΔR/(4R) = 562.5 mV is 12.5 % too high: a quarter bridge is not quite linear.

12.Wheatstone bridge & strain gauges

Answer: Vo = 0.375 mV

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Relative resistance change

ΔR/R = 2·250·10⁻⁶ = 0.0005

Bridge output

Vo ≈ Vs·GF·ε/4 = 3·0.0005/4 = 0.375 mV

Answer

Vo = 0.375 mV
13.Digital logic: gates, K-maps & flip-flops

Answer: L = 4

Boolean algebra: the rules that simplify expressions are X + X′ = 1 and X·X′ = 0, X + X = X, absorption X + X·Y = X, the combining rule X·Y + X·Y′ = X, X + X′Y = X + Y and the consensus theorem XY + X′Z + YZ = XY + X′Z. De Morgan's laws turn (X·Y)′ into X′ + Y′ and (X + Y)′ into X′·Y′. A Karnaugh map applies these rules graphically: every group of two neighbouring cells is one use of XY + XY′ = X.

Minterms of the expression

AC′ → m(4, 6)
BC → m(3, 7)
ABC′ → m(6)
ABC00011110010001130214051716

Group and read off

F = BC + AC′

Count the literals

L = 4

Answer

L = 4
14.Digital logic: gates, K-maps & flip-flops

Answer: Q = 10

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Full cycles

Every 16 pulses bring the counter back to the same state.

43 = 2·16 + 11

Count after the remaining pulses

Q = (15 + 11) mod 16 = 10
Q = 1010₂

Answer

Q = 10

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