Electronics 1: cram pack

Zener regulator: a reverse-biased Zener diode holds its voltage V_Z while its current stays above a minimum I_Z,min. The series resistor R takes the difference between input and output: I_R = (V_in − V_Z)/R. That current splits between the load, I_L = V_Z/R_L, and the Zener: I_Z = I_R − I_L. Design for the worst cases: the lowest input with the largest load must still leave I_Z,min, and the highest input with no load gives the largest Zener power P_Z = V_Z·I_Z.

Zener regulator: a reverse-biased Zener diode holds its voltage V_Z while its current stays above a minimum I_Z,min. The series resistor R takes the difference between input and output: I_R = (V_in − V_Z)/R. That current splits between the load, I_L = V_Z/R_L, and the Zener: I_Z = I_R − I_L. Design for the worst cases: the lowest input with the largest load must still leave I_Z,min, and the highest input with no load gives the largest Zener power P_Z = V_Z·I_Z.

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e^−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e^−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck V_o = D·V_in, boost V_o = V_in/(1 − D), inverting buck-boost |V_o| = V_in·D/(1 − D). An ideal converter keeps the power: V_in·I_in = V_o·I_o. While S is on the inductor current rises by ΔI_L = V_L·D·T/L, with V_L = V_in − V_o for the buck and V_in for the boost and buck-boost. The output ripple is ΔV_o = ΔI_L/(8fC) for the buck and I_o·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔI_L/2.

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck V_o = D·V_in, boost V_o = V_in/(1 − D), inverting buck-boost |V_o| = V_in·D/(1 − D). An ideal converter keeps the power: V_in·I_in = V_o·I_o. While S is on the inductor current rises by ΔI_L = V_L·D·T/L, with V_L = V_in − V_o for the buck and V_in for the boost and buck-boost. The output ripple is ΔV_o = ΔI_L/(8fC) for the buck and I_o·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔI_L/2.

Wheatstone bridge: two voltage dividers share one supply V_s. The left divider R₁–R₂ gives V_a = V_s·R₂/(R₁ + R₂) and the right divider R₃–R₄ gives V_b = V_s·R₄/(R₃ + R₄); the output is V_ab = V_a − V_b. The bridge is balanced (V_ab = 0, no current in the meter) when R₁/R₂ = R₃/R₄, that is R₁·R₄ = R₂·R₃. Seen from the output, the bridge is a Thévenin source with R_th = R₁∥R₂ + R₃∥R₄.

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives V_o ≈ V_s·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give V_s·GF·ε/2, and four (full bridge) give V_s·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at f_clk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.