Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

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1Formulas and methods

Diodes & transistors

Diode (constant drop)
VD = 0.7 V when conducting
Active region
VBE = 0.7 V, IC = β·IB, IE = (β + 1)·IB
Fixed bias
IB = (VCC − 0.7)/RB
Divider bias
IB = (VTH − 0.7)/(RTH + (β + 1)RE)
Thévenin of the divider
VTH = VCC·R2/(R1 + R2), RTH = R1∥R2
Collector loop
VCE = VCC − ICRC − IERE
Saturation
IC(sat) = (VCC − VCE(sat))/RC, IB ≥ IC(sat)/β

Op-amp circuits

Inverting amplifier
Vout = −(Rf/Rin)·Vin
Non-inverting amplifier
Vout = (1 + Rf/R1)·Vin
Summing amplifier
Vout = −Rf(V1/R1 + V2/R2)
Ideal op-amp
V+ = V−, Iin = 0

RC & RL transients

Time constant
τ = RC | τ = L/R
Response
x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ
Capacitor at DC
open circuit; vC cannot jump
Inductor at DC
short circuit; iL cannot jump
Settled
t ≈ 5τ

Method

  1. Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
  2. Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
  3. Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
  4. Use x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ.

Series & parallel resistors

Resistors in series
Req = R1 + R2 + …
Resistors in parallel
1/Req = 1/R1 + 1/R2 + …
Two in parallel
Req = R1R2 / (R1 + R2)
Ohm's law
V = I·R
Power
P = V·I = I²R = V²/R

Method

  1. Start at the end of the network furthest from the terminals.
  2. Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
  3. Redraw the circuit after each step.
  4. Repeat until one resistor is left between the terminals.

DC-DC converters

Buck
Vo = D·Vin
Boost
Vo = Vin/(1 − D)
Inverting buck-boost
|Vo| = Vin·D/(1 − D)
Ideal power balance
VinIin = VoIo
Inductor ripple
ΔIL = VL,on·D/(L·f); buck Vin − Vo, boost and buck-boost Vin
Average inductor current
buck Io; boost and buck-boost Io/(1 − D)
Output ripple
buck ΔIL/(8fC); boost and buck-boost Io·D/(fC)
CCM boundary
buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

  1. Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
  2. Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
  3. Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
  4. For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.

Wheatstone bridge & strain gauges

Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε

Method

  1. Treat the bridge as two voltage dividers across the same supply.
  2. For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
  3. For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
  4. For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium
RC​ = 3.3 kΩβ = 120RE​ = 2.2 kΩVCC​ = 15 VR1​ = 22 kΩR2​ = 6.8 kΩ

An NPN transistor with β = 120 has voltage-divider bias from VCC = 15 V: R₁ = 22 kΩ from VCC to the base and R₂ = 6.8 kΩ from the base to ground. The collector resistor is RC = 3.3 kΩ and the emitter resistor is RE = 2.2 kΩ. Take VBE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector–emitter voltage VCE.

VCC = 15 VR1 = 22 kΩR2 = 6.8 kΩRC = 3.3 kΩRE = 2.2 kΩβ = 120
VCE = V
2.Diodes & transistorsHard
RC​ = 220 Ωβ = 80IC​ = ?VCC​ = 5 V5 VRB​ = 4.7 kΩ

An NPN transistor with β = 80 switches a 220 Ω load resistor connected between VCC = 5 V and its collector. The emitter is grounded. The base is driven from a 5 V logic output through a base resistor RB = 4.7 kΩ. Take VBE = 0.7 V and VCE(sat) = 0.2 V. Find the collector current IC in mA when the input is high. Decide first whether the transistor is saturated.

VCC = 5 VRC = 220 Ωβ = 80Vin = 5 VVBE = 0.7 VVCE(sat) = 0.2 VRB = 4.7 kΩ
IC = mA
3.Op-amp circuitsMedium
−+Vout​R2​ = 2 kΩV1​ = −1.8 VR1​ = 4.7 kΩV2​ = 2.5 VR3​ = 4.7 kΩR4​ = 2 kΩ

The difference amplifier uses an ideal op-amp with ±15 V supplies, with R3 = R1 and R4 = R2. Find the output voltage Vout.

V1 = −1.8 VV2 = 2.5 VR1 = R3 = 4.7 kΩR2 = R4 = 2 kΩ
Vout = V
4.Op-amp circuitsHard
−+Vout​Rf​ = 4.7 kΩV1​ = −0.7 VR1​ = 2 kΩV2​ = 0.9 VR2​ = 47 kΩ

The summing amplifier uses an ideal op-amp with ±15 V supplies. Find the output voltage Vout.

V1 = −0.7 VV2 = 0.9 VR1 = 2 kΩR2 = 47 kΩRf = 4.7 kΩ
Vout = V
5.RC & RL transientsMedium
R = 68 Ωt = 0L22 mHi(t)

The inductor carries a steady current of 1.5 A. At t = 0 the switch closes the loop through R and the source is removed, so the inductor current decays through R. How long does it take for the current to fall to 0.375 A? Find t.

i(0) = 1.5 AR = 68 ΩL = 22 mH
t = ms
6.RC & RL transientsHard
+−Vs​24 Vt = 0R = 6.8 kΩC10 µF+−vC​vC​(0) = 12 V

Just before the switch closes at t = 0, the capacitor holds 12 V with the polarity shown. How long does it take for vC to reach 20.4 V? Find t.

Vs = 24 VR = 6.8 kΩC = 10 µFvC(0) = 12 V
t = ms
7.Series & parallel resistorsMedium
R1​ = 3 ΩIR1​R3​ = 2 Ω+−V1​18 VR2​10 ΩAR4​3 ΩB

Find the current IR1 delivered by the source, which flows through R1.

V1 = 18 VR1 = 3 ΩR2 = 10 ΩR3 = 2 ΩR4 = 3 Ω
IR1 = A
8.Series & parallel resistorsHard
R1​ = 20 ΩR3​ = 10 ΩR5​ = 4 Ω+−V1​15 VR2​5 ΩIR2​AR4​8 ΩBR6​15 Ω

Find the current IR2 through R2.

V1 = 15 VR1 = 20 ΩR2 = 5 ΩR3 = 10 ΩR4 = 8 ΩR5 = 4 ΩR6 = 15 Ω
IR2 = A
9.DC-DC convertersMedium
tiL​Imax​Imin​ΔI = ?DTT2T

An ideal buck converter turns 15 V into 7.5 V at 100 kHz with L = 220 µH. Find the peak-to-peak inductor ripple current ΔIL.

Vin​ = 15 VVo​ = 7.5 Vf = 100 kHzL = 220 µH
ΔIL = A
10.DC-DC convertersHard
tiL​Imax​IL​DTT2T

An ideal inverting buck-boost converter turns 48 V into −16 V for a 4 Ω load at 50 kHz. Find the smallest inductance Lcrit for continuous conduction.

Vin​ = 48 VVo​ = −16 Vf = 50 kHzR = 4 Ω
Lcrit = µH
11.Wheatstone bridge & strain gaugesMedium
+−3 V470 Ω470 Ω + ΔR470 Ω470 Ωab+−Vab​ = ?

A bridge has four 470 Ω arms and Vs = 3 V. The sensor R₂ increases by ΔR = 117.5 Ω. Find the exact output Vab in mV.

Vs = 3 VR = 470 ΩΔR = 117.5 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
+−5 V350 Ω350 Ω + ΔR350 Ω350 Ωab+−Vo​

A quarter bridge (one active gauge, GF = 2) is excited with 5 V. The largest strain to be measured is 250 µε, and it must give 10 V at the input of an analogue-to-digital converter. Find the amplifier gain G.

Vs = 5 VGF = 2εmax = 250 µεVFS = 10 V
G =
13.Digital logic: gates, K-maps & flip-flopsMedium
ABCD000111100001111010010312041517060121131151141809011110

Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C, D) = Σm(0, 2, 5, 7, 8, 10, 13, 14, 15). How many literals L does it contain in total (a primed variable counts as one literal)?

F(A, B, C, D) = Σm(0, 2, 5, 7, 8, 10, 13, 14, 15)
L =
14.Digital logic: gates, K-maps & flip-flopsHard
ABCD000111100001111000111302140517X6112X13115X140809011010

Find the minimal SOP form of F(A, B, C, D) = Σm(1, 3, 4, 7, 12, 15) + d(6, 13, 14), where d marks the don't-care conditions. How many literals L does it contain?

F(A, B, C, D) = Σm(1, 3, 4, 7, 12, 15) + d(6, 13, 14)
L =

3Solutions

1.Diodes & transistors

Answer: VCE = 8.066 V

BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.

Thévenin equivalent of the divider

VTH = 15·6.8/(22 + 6.8) = 3.542 V
RTH = 22·6.8/(22 + 6.8) = 5.194 kΩ

Base current

KVL around the base loop; the emitter current is (β + 1)·IB.

IB = (3.542 − 0.7)/(5.194 + 121·2.2) = 10.47 µA

Collector current

IC = 120·10.47 µA = 1.256 mA
IE = 121·10.47 µA = 1.267 mA

Collector–emitter voltage

VCE = 15 − 1.256·3.3 − 1.267·2.2 = 8.066 V

Answer

VCE = 8.066 V
2.Diodes & transistors

Answer: IC = 21.82 mA

BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.

Base current

IB = (5 − 0.7)/4.7 kΩ = 914.9 µA

Saturated or active?

β·IB is larger than IC(sat), so the transistor saturates.

β·IB = 73.19 mA
IC(sat) = (5 − 0.2)/220 = 21.82 mA

Collector current

IC = IC(sat) = 21.82 mA

Answer

IC = 21.82 mA

The transistor is saturated.

3.Op-amp circuits

Answer: Vout = 1.83 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Voltage at the inputs

R₃ and R₄ carry the same current, so they form a voltage divider; feedback makes V₋ = V₊.

V₊ = V2·R4/(R3 + R4) = 2.5·2/(4.7 + 2) = 0.7463 V
V₋ = V₊

KCL at the inverting input

(−1.8 − 0.7463)/4.7 = (0.7463 − Vout)/2
Vout = (R2/R1)·(V2 − V1) = (2/4.7)·(2.5 − (−1.8)) = 1.83 V

Answer

Vout = 1.83 V
4.Op-amp circuits

Answer: Vout = 1.555 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Input currents

V₋ = 0, so each input resistor has its full input voltage across it.

I1 = V1/R1 = −0.7/2 = −0.35 mA
I2 = V2/R2 = 0.9/47 = 0.01915 mA
If = I1 + I2 = −0.3309 mA

Output voltage

Vout = −Rf·If = −4.7·(−0.3309) = 1.555 V

Answer

Vout = 1.555 V
5.RC & RL transients

Answer: t = 0.4485 ms

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Time constant

τ = L/R = 22 mH / 68 Ω = 0.3235 ms

Solve for the time

0.375 = 1.5·e−t/τ → t = τ·ln(1.5/0.375)
t = 0.3235·ln(4) = 0.4485 ms

Answer

t = 0.4485 ms
6.RC & RL transients

Answer: t = 81.87 ms

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Initial value, final value, time constant

The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.

vC(0) = 12 V, vC(∞) = Vs = 24 V
τ = R·C = 6.8 kΩ · 10 µF = 68 ms
vC(t) = 24 + (12 − 24)·e−t/τ

Solve for the time

20.4 = 24 + (−12)·e−t/τ → e−t/τ = (20.4 − 24)/(12 − 24) = 0.3
t = τ·ln((12 − 24)/(20.4 − 24)) = 68·ln(3.333) = 81.87 ms

Answer

t = 81.87 ms
7.Series & parallel resistors

Answer: IR1 = 2.842 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 3 ΩR3​ = 2 Ω+−V1​18 VR2​10 ΩAR4​3 ΩB

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R3 + R4 = 2 + 3 = 5 Ω
R2 ∥ 5 = 10·5/(10+5) = 3.333 Ω
Req = R1 + 3.333 = 3 + 3.333 = 6.333 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 18/6.333 = 2.842 A

Answer

IR1 = 2.842 A
8.Series & parallel resistors

Answer: IR2 = 0.4777 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 20 ΩR3​ = 10 ΩR5​ = 4 Ω+−V1​15 VR2​5 ΩAR4​8 ΩBR6​15 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R5 + R6 = 4 + 15 = 19 Ω
R4 ∥ 19 = 5.63 Ω
R3 + 5.63 = 15.63 Ω
R2 ∥ 15.63 = 3.788 Ω
Req = R1 + 3.788 = 20 + 3.788 = 23.79 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 15/23.79 = 0.6306 A

Current through R₂

Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.

VA = V1 − IR1·R1 = 15 − 0.6306·20 = 2.389 V
IR2 = VA/R2 = 2.389/5 = 0.4777 A

Answer

IR2 = 0.4777 A
9.DC-DC converters

Answer: ΔIL = 0.1705 A

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 7.5/15 = 0.5

Inductor voltage during the on-time

While S is on, the inductor sits between Vin and Vo.

VL = 15 − 7.5 = 7.5 V

Ripple current

ΔIL = VL·D/(L·f) = 7.5·0.5/(220·10⁻⁶·100·10³) = 0.1705 A

Answer

ΔIL = 0.1705 A
10.DC-DC converters

Answer: Lcrit = 22.5 µH

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 16/(48 + 16) = 0.25

Boundary condition

Set the average inductor current equal to half the ripple current and solve for L.

Lcrit = (1 − D)²·R/(2f)

Critical inductance

Lcrit = (1 − 0.25)²·4/(250·10³) = 22.5 µH

Answer

Lcrit = 22.5 µH
11.Wheatstone bridge & strain gauges

Answer: Vab = 166.7 mV

Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.

Node voltages

Va = 3·587.5/1058 = 1.667 V
Vb = 1.5 V

Output

Vab = 166.7 mV

Answer

Vab = 166.7 mV

The linear estimate Vs·ΔR/(4R) = 187.5 mV is 12.5 % too high: a quarter bridge is not quite linear.

12.Wheatstone bridge & strain gauges

Answer: G = 16000

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Bridge output at full scale

Vo = 0.625 mV

Gain

G = 10/0.000625 = 16000

Answer

G = 16000
13.Digital logic: gates, K-maps & flip-flops

Answer: L = 7

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

ABCD000111100001111010010312041517060121131151141809011110

Group the 1s

Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.

B′D′
BD
ACD′

Minimal SOP form

F = B′D′ + BD + ACD′
L = 7

Answer

L = 7

Another grouping of the same size exists; it has the same number of terms and literals.

14.Digital logic: gates, K-maps & flip-flops

Answer: L = 7

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Prime implicants

The largest groups that can be formed from 1s and Xs.

BD′, BC, A′CD, AB, A′B′D
ABCD000111100001111000111302140517X6112X13115X140809011010

Minimal cover

F = BD′ + BC + A′B′D
L = 7

Answer

L = 7

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