Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

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1Formulas and methods

Diodes & transistors

Diode (constant drop)
VD = 0.7 V when conducting
Active region
VBE = 0.7 V, IC = β·IB, IE = (β + 1)·IB
Fixed bias
IB = (VCC − 0.7)/RB
Divider bias
IB = (VTH − 0.7)/(RTH + (β + 1)RE)
Thévenin of the divider
VTH = VCC·R2/(R1 + R2), RTH = R1∥R2
Collector loop
VCE = VCC − ICRC − IERE
Saturation
IC(sat) = (VCC − VCE(sat))/RC, IB ≥ IC(sat)/β

Op-amp circuits

Inverting amplifier
Vout = −(Rf/Rin)·Vin
Non-inverting amplifier
Vout = (1 + Rf/R1)·Vin
Summing amplifier
Vout = −Rf(V1/R1 + V2/R2)
Ideal op-amp
V+ = V−, Iin = 0

RC & RL transients

Time constant
τ = RC | τ = L/R
Response
x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ
Capacitor at DC
open circuit; vC cannot jump
Inductor at DC
short circuit; iL cannot jump
Settled
t ≈ 5τ

Method

  1. Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
  2. Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
  3. Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
  4. Use x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ.

Series & parallel resistors

Resistors in series
Req = R1 + R2 + …
Resistors in parallel
1/Req = 1/R1 + 1/R2 + …
Two in parallel
Req = R1R2 / (R1 + R2)
Ohm's law
V = I·R
Power
P = V·I = I²R = V²/R

Method

  1. Start at the end of the network furthest from the terminals.
  2. Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
  3. Redraw the circuit after each step.
  4. Repeat until one resistor is left between the terminals.

DC-DC converters

Buck
Vo = D·Vin
Boost
Vo = Vin/(1 − D)
Inverting buck-boost
|Vo| = Vin·D/(1 − D)
Ideal power balance
VinIin = VoIo
Inductor ripple
ΔIL = VL,on·D/(L·f); buck Vin − Vo, boost and buck-boost Vin
Average inductor current
buck Io; boost and buck-boost Io/(1 − D)
Output ripple
buck ΔIL/(8fC); boost and buck-boost Io·D/(fC)
CCM boundary
buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

  1. Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
  2. Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
  3. Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
  4. For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.

Wheatstone bridge & strain gauges

Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε

Method

  1. Treat the bridge as two voltage dividers across the same supply.
  2. For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
  3. For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
  4. For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium
+−18 V270 Ω9.1 V1500 ΩIZ​ = ?

A 9.1 V Zener regulator is fed from 18 V through 270 Ω and supplies a 1500 Ω load. Find the Zener current IZ.

Vin = 18 VVZ = 9.1 VR = 270 ΩRL = 1500 Ω
IZ = mA
2.Diodes & transistorsHard
RC​ = 330 Ωβ = 80VCC​ = 24 V5 VRB​ = ?

An NPN transistor with β = 80 switches a 330 Ω load resistor connected between VCC = 24 V and its collector. The emitter is grounded. The base is driven from a 5 V logic output through a base resistor RB. Take VBE = 0.7 V and VCE(sat) = 0.2 V. For reliable switching, design for a base current 10 times the minimum needed for saturation. Find RB in kΩ.

VCC = 24 VRC = 330 Ωβ = 80Vin = 5 VVBE = 0.7 VVCE(sat) = 0.2 Voverdrive = 10
RB = kΩ
3.Op-amp circuitsMedium
−+Vout​Rf​ = 47 kΩR1​ = 10 kΩVin​ = 0.9 V

The op-amp is ideal and runs from ±15 V supplies. Find the output voltage Vout.

Vin = 0.9 VR1 = 10 kΩRf = 47 kΩ
Vout = V
4.Op-amp circuitsHard
Vin​V1​Vout​stage 1: invertingR1​ = 4.7 kΩRf1​ = 22 kΩstage 2: non-invertingR2​ = 47 kΩRf2​ = 10 kΩ

Two ideal op-amp stages are connected in cascade: an inverting amplifier (R1, Rf1) followed by a non-inverting amplifier (R2 to ground, Rf2 in the feedback). Both run from ±15 V supplies. The input is Vin = 0.2 V. Find the output voltage Vout.

R1 = 4.7 kΩRf1 = 22 kΩR2 = 47 kΩRf2 = 10 kΩVin = 0.2 V
Vout = V
5.RC & RL transientsMedium
+−Vs​20 Vt = 0R = 20 ΩL22 mHi(t)

The inductor carries no current before the switch closes at t = 0. How long after the switch closes does the current reach 50% of its final value? Find t.

Vs = 20 VR = 20 ΩL = 22 mH
t = ms
6.RC & RL transientsHard
+−Vs​24 Vt = 0R = 10 kΩC220 µF+−vC​vC​(0) = 15 V

Just before the switch closes at t = 0, the capacitor holds 15 V with the polarity shown. How long does it take for vC to reach 22.2 V? Find t.

Vs = 24 VR = 10 kΩC = 220 µFvC(0) = 15 V
t = ms
7.Series & parallel resistorsMedium
R1​ = 12 ΩIR1​R3​ = 4 Ω+−V1​18 VR2​3 ΩAR4​12 ΩB

Find the current IR1 delivered by the source, which flows through R1.

V1 = 18 VR1 = 12 ΩR2 = 3 ΩR3 = 4 ΩR4 = 12 Ω
IR1 = A
8.Series & parallel resistorsHard
R1​ = 25 ΩR3​ = 10 ΩR5​ = 12 Ω+−V1​36 VR2​2 ΩIR2​AR4​20 ΩBR6​6 Ω

Find the current IR2 through R2.

V1 = 36 VR1 = 25 ΩR2 = 2 ΩR3 = 10 ΩR4 = 20 ΩR5 = 12 ΩR6 = 6 Ω
IR2 = A
9.DC-DC convertersMedium
tiL​Imax​Imin​ΔI = ?DTT2T

An ideal buck converter turns 9 V into 2.7 V at 40 kHz with L = 100 µH. Find the peak-to-peak inductor ripple current ΔIL.

Vin​ = 9 VVo​ = 2.7 Vf = 40 kHzL = 100 µH
ΔIL = A
10.DC-DC convertersHard
+−12 VSL = 68 µHC = ?R+−9 V

A buck converter turns 12 V into 9 V at 50 kHz with L = 68 µH. Find the output capacitance C that limits the peak-to-peak output ripple to 50 mV.

Vin​ = 12 VVo​ = 9 Vf = 50 kHzL = 68 µHΔVo = 50 mV
C = µF
11.Wheatstone bridge & strain gaugesMedium
+−15 V200 Ω200 Ω + ΔR200 Ω200 Ωab+−357.1 mV

A bridge with four 200 Ω arms is supplied with 15 V. When the sensor R₂ changes, the output reads Vab = 357.1 mV. Find the exact change ΔR of R₂.

Vs = 15 VR = 200 ΩVab = 357.1 mV
ΔR = Ω
12.Wheatstone bridge & strain gaugesHard
+−10 V350 Ω350 Ω + ΔR350 Ω350 Ωab+−3.844 mV

A quarter bridge with one active gauge (GF = 2.05) is excited with 10 V. Under load the output reads 3.844 mV. Find the strain ε in µε.

Vs = 10 VGF = 2.05Vo = 3.844 mV
ε = µε
13.Digital logic: gates, K-maps & flip-flopsMedium
ABCD0001111000011110111111

In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.

F = Σm(1, 2, 3, 5, 9, 15)
  1. 1AB = 00, CD = 00
  2. 2AB = 00, CD = 01
  3. 3AB = 00, CD = 11
  4. 4AB = 00, CD = 10
  5. 5AB = 01, CD = 00
  6. 6AB = 01, CD = 01
  7. 7AB = 01, CD = 11
  8. 8AB = 01, CD = 10
  9. 9AB = 11, CD = 00
  10. 10AB = 11, CD = 01
  11. 11AB = 11, CD = 11
  12. 12AB = 11, CD = 10
  13. 13AB = 10, CD = 00
  14. 14AB = 10, CD = 01
  15. 15AB = 10, CD = 11
  16. 16AB = 10, CD = 10
14.Digital logic: gates, K-maps & flip-flopsHard
ABCD00011110000111100011X302041517060121130151140819X11010

Find the minimal SOP form of F(A, B, C, D) = Σm(1, 5, 7, 9, 13, 14) + d(3, 11), where d marks the don't-care conditions. How many literals L does it contain?

F(A, B, C, D) = Σm(1, 5, 7, 9, 13, 14) + d(3, 11)
L =

3Solutions

1.Diodes & transistors

Answer: IZ = 26.9 mA

Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.

Resistor current

IR = 8.9/270 = 32.96 mA

Load current

IL = 9.1/1500 = 6.067 mA

Zener current

IZ = 32.96 − 6.067 = 26.9 mA

Answer

IZ = 26.9 mA
2.Diodes & transistors

Answer: RB = 0.477 kΩ

BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.

Collector current in saturation

IC(sat) = (24 − 0.2)/330 = 72.12 mA

Minimum base current

IB(min) = IC(sat)/β = 72.12/80 = 901.5 µA

Design base current

IB = 10·901.5 µA = 9015 µA

Base resistor

RB = (5 − 0.7)/IB = 4.3 V/9.015 mA = 0.477 kΩ

Answer

RB = 0.477 kΩ
3.Op-amp circuits

Answer: Vout = 5.13 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Inverting input follows the input

V₋ = V₊ = 0.9 V
I = V₋/R1 = 0.9/10 = 0.09 mA

Output voltage

The current through R₁ also flows through Rf.

Vout = V₋ + I·Rf = 0.9 + 0.09·47 = 5.13 V

Answer

Vout = 5.13 V
4.Op-amp circuits

Answer: Vout = −1.135 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Gain of each stage

A1 = −Rf1/R1 = −22/4.7 = −4.681
A2 = 1 + Rf2/R2 = 1 + 10/47 = 1.213

Stage by stage

V1 = −4.681·0.2 = −0.9362 V
Vout = 1.213·(−0.9362) = −1.135 V

Answer

Vout = −1.135 V
5.RC & RL transients

Answer: t = 0.7625 ms

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Time constant and final current

Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.

τ = L/R = 22 mH / 20 Ω = 1.1 ms
i(∞) = Vs/R = 20/20 = 1 A

Solve for the time

0.5 = 1 − e−t/τ → t = −τ·ln(1 − 0.5)
t = −1.1·ln(0.5) = 0.7625 ms

Answer

t = 0.7625 ms
6.RC & RL transients

Answer: t = 3541 ms

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Initial value, final value, time constant

The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.

vC(0) = 15 V, vC(∞) = Vs = 24 V
τ = R·C = 10 kΩ · 220 µF = 2200 ms
vC(t) = 24 + (15 − 24)·e−t/τ

Solve for the time

22.2 = 24 + (−9)·e−t/τ → e−t/τ = (22.2 − 24)/(15 − 24) = 0.2
t = τ·ln((15 − 24)/(22.2 − 24)) = 2200·ln(5) = 3541 ms

Answer

t = 3541 ms
7.Series & parallel resistors

Answer: IR1 = 1.239 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 12 ΩR3​ = 4 Ω+−V1​18 VR2​3 ΩAR4​12 ΩB

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R3 + R4 = 4 + 12 = 16 Ω
R2 ∥ 16 = 3·16/(3+16) = 2.526 Ω
Req = R1 + 2.526 = 12 + 2.526 = 14.53 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 18/14.53 = 1.239 A

Answer

IR1 = 1.239 A
8.Series & parallel resistors

Answer: IR2 = 1.218 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 25 ΩR3​ = 10 ΩR5​ = 12 Ω+−V1​36 VR2​2 ΩAR4​20 ΩBR6​6 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R5 + R6 = 12 + 6 = 18 Ω
R4 ∥ 18 = 9.474 Ω
R3 + 9.474 = 19.47 Ω
R2 ∥ 19.47 = 1.814 Ω
Req = R1 + 1.814 = 25 + 1.814 = 26.81 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 36/26.81 = 1.343 A

Current through R₂

Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.

VA = V1 − IR1·R1 = 36 − 1.343·25 = 2.435 V
IR2 = VA/R2 = 2.435/2 = 1.218 A

Answer

IR2 = 1.218 A
9.DC-DC converters

Answer: ΔIL = 0.4725 A

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 2.7/9 = 0.3

Inductor voltage during the on-time

While S is on, the inductor sits between Vin and Vo.

VL = 9 − 2.7 = 6.3 V

Ripple current

ΔIL = VL·D/(L·f) = 6.3·0.3/(100·10⁻⁶·40·10³) = 0.4725 A

Answer

ΔIL = 0.4725 A
10.DC-DC converters

Answer: C = 33.09 µF

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 9/12 = 0.75

Inductor ripple current

ΔIL = (12 − 9)·0.75/(68·10⁻⁶·50·10³) = 0.6618 A

Capacitance

C = 0.6618/(8·50·10³·50·10⁻³) = 33.09 µF

Answer

C = 33.09 µF
11.Wheatstone bridge & strain gauges

Answer: ΔR = 20 Ω

Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.

Node voltage

Va = 7.5 + 0.3571 = 7.857 V

Solve the divider

R₂ = 200·7.857/(15 − 7.857) = 220 Ω
ΔR = 220 − 200 = 20 Ω

Answer

ΔR = 20 Ω
12.Wheatstone bridge & strain gauges

Answer: ε = 750 µε

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Solve the quarter-bridge equation

ε = 4·0.003844/(10·2.05) = 0.00075

In microstrain

ε = 750 µε

Answer

ε = 750 µε
13.Digital logic: gates, K-maps & flip-flops

Answer: AB = 11, CD = 11

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Neighbours of each 1

A 1 with a neighbouring 1 can join a group of two or more.

m15: m14, m13, m11, m7 → 0
ABCD0001111000011110111111

The isolated 1

m15 = ABCD → AB = 11, CD = 11

Answer

AB = 11, CD = 11
14.Digital logic: gates, K-maps & flip-flops

Answer: L = 8

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Prime implicants

The largest groups that can be formed from 1s and Xs.

C′D, B′D, A′D, ABCD′
ABCD00011110000111100011X302041517060121130151140819X11010

Minimal cover

F = C′D + A′D + ABCD′
L = 8

Answer

L = 8

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