Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 200 has voltage-divider bias from VCC = 18 V: R₁ = 39 kΩ from VCC to the base and R₂ = 4.7 kΩ from the base to ground. The collector resistor is RC = 1 kΩ and the emitter resistor is RE = 680 Ω. Take VBE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector–emitter voltage VCE.
An NPN transistor with β = 50 switches a 100 Ω load resistor connected between VCC = 5 V and its collector. The emitter is grounded. The base is driven from a 5 V logic output through a base resistor RB. Take VBE = 0.7 V and VCE(sat) = 0.2 V. For reliable switching, design for a base current 3 times the minimum needed for saturation. Find RB in kΩ.
The source Vₛ charges the capacitor through R₁, and R₂ is connected in parallel with C. The capacitor is uncharged when the switch closes at t = 0. Find the capacitor voltage vC at t = 120 ms.
Vs = 9 VR1 = 1 kΩR2 = 10 kΩC = 47 µFt = 120 ms
vC = V
6.RC & RL transientsHard
The switch across R2 has been open for a long time, so the inductor current is steady. At t = 0 the switch closes and shorts out R2. Find the inductor current i at t = 5 ms.
Vs = 9 VR1 = 5 ΩR2 = 5 ΩL = 47 mHt = 5 ms
i = A
7.Series & parallel resistorsMedium
Find the current IR1 delivered by the source, which flows through R1.
V1 = 18 VR1 = 20 ΩR2 = 8 ΩR3 = 5 ΩR4 = 15 Ω
IR1 = A
8.Series & parallel resistorsHard
Find the equivalent resistance Req seen by the source V1.
An ideal inverting buck-boost converter turns 12 V into −18 V at 25 kHz with L = 150 µH. Find the peak-to-peak inductor ripple current ΔIL.
Vin = 12 VVo = −18 Vf = 25 kHzL = 150 µH
ΔIL = A
10.DC-DC convertersHard
A buck converter turns 15 V into 10.5 V at 50 kHz with L = 330 µH. Find the smallest load current Io,min for which it stays in continuous conduction.
Vin = 15 VVo = 10.5 Vf = 50 kHzL = 330 µH
Io,min = A
11.Wheatstone bridge & strain gaugesMedium
A 200 Ω strain gauge is one arm (R₂) of a bridge with four equal 200 Ω arms and an excitation of 10 V. Find the power Pg dissipated in the gauge, in mW. Self-heating limits the excitation.
Vs = 10 VR = 200 Ω
Pg = mW
12.Wheatstone bridge & strain gaugesHard
A strain gauge (GF = 2) on a member with E = 70 GPa forms a quarter bridge excited with 10 V. The output reads 2 mV. Find the axial stress σ in MPa.
A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = 1, I₁ = C, I₂ = C, I₃ = C. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.
I₀ = 1I₁ = CI₂ = CI₃ = C
N =
14.Digital logic: gates, K-maps & flip-flopsHard
For F(A, B, C, D) = Σm(2, 4, 9, 10, 14) + d(7, 11), where d marks the don't-care conditions, find the number N of essential prime implicants.
F(A, B, C, D) = Σm(2, 4, 9, 10, 14) + d(7, 11)
N =
3Solutions
1.Diodes & transistors
Answer: VCE = 15.05 V
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Thévenin equivalent of the divider
VTH = 18·4.7/(39 + 4.7) = 1.936 V
RTH = 39·4.7/(39 + 4.7) = 4.195 kΩ
Base current
KVL around the base loop; the emitter current is (β + 1)·IB.
IB = (1.936 − 0.7)/(4.195 + 201·0.68) = 8.773 µA
Collector current
IC = 200·8.773 µA = 1.755 mA
IE = 201·8.773 µA = 1.763 mA
Collector–emitter voltage
VCE = 18 − 1.755·1 − 1.763·0.68 = 15.05 V
Answer
VCE = 15.05 V
2.Diodes & transistors
Answer: RB = 1.493 kΩ
BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.
Collector current in saturation
IC(sat) = (5 − 0.2)/100 = 48 mA
Minimum base current
IB(min) = IC(sat)/β = 48/50 = 960 µA
Design base current
IB = 3·960 µA = 2880 µA
Base resistor
RB = (5 − 0.7)/IB = 4.3 V/2.88 mA = 1.493 kΩ
Answer
RB = 1.493 kΩ
3.Op-amp circuits
Answer: Rf = 4 kΩ
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain of a non-inverting amplifier
V₋ = V₊ = Vin, and the current through R₁ also flows through Rf, so Vout = Vin·(1 + Rf/R₁).
Av = 1 + Rf/R1
Rf = (3 − 1)·2 = 4 kΩ
Answer
Rf = 4 kΩ
4.Op-amp circuits
Answer: Vout = 0.2049 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Voltage at the + input
V₊ = V2·R4/(R3 + R4) = 1.8·1/(10 + 1) = 0.1636 V
Superpose the two inputs
With V₂ = 0, V₁ sees an inverting amplifier. With V₁ = 0, V₊ is amplified by the non-inverting gain 1 + R₂/R₁.
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Thévenin equivalent seen by the capacitor
Short the source to find Rth; open the capacitor to find the voltage it will settle at.
Rth = R1 ∥ R2 = 1·10/(1 + 10) = 0.9091 kΩ
vC(∞) = 9·10/(1 + 10) = 8.182 V
Time constant
τ = Rth·C = 0.9091·47 = 42.73 ms
Charging curve
vC(t) = 8.182·(1 − e−120/42.73) = 7.688 V
Answer
vC = 7.688 V
6.RC & RL transients
Answer: i = 1.271 A
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial value, final value, time constant
Before t = 0 both resistors are in the loop; afterwards the closed switch bypasses R₂.
i(0) = 9/(5 + 5) = 0.9 A
i(∞) = 9/5 = 1.8 A
τ = L/R = 47/5 = 9.4 ms
i(t) = 1.8 + (0.9 − 1.8)·e−t/τ
Current at the given time
i(5) = 1.8 + (−0.9)·e−5/9.4 = 1.271 A
Answer
i = 1.271 A
7.Series & parallel resistors
Answer: IR1 = 0.7 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 5 + 15 = 20 Ω
R2 ∥ 20 = 8·20/(8+20) = 5.714 Ω
Req = R1 + 5.714 = 20 + 5.714 = 25.71 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 18/25.71 = 0.7 A
Answer
IR1 = 0.7 A
8.Series & parallel resistors
Answer: Req = 13.14 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 15 + 15 = 30 Ω
R4 ∥ 30 = 5 Ω
R3 + 5 = 9 Ω
R2 ∥ 9 = 5.143 Ω
Req = R1 + 5.143 = 8 + 5.143 = 13.14 Ω
Answer
Req = 13.14 Ω
9.DC-DC converters
Answer: ΔIL = 1.92 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 18/(12 + 18) = 0.6
Inductor voltage during the on-time
While S is on, the inductor sits directly across Vin.
VL = 12 V
Ripple current
ΔIL = VL·D/(L·f) = 12·0.6/(150·10⁻⁶·25·10³) = 1.92 A
Answer
ΔIL = 1.92 A
10.DC-DC converters
Answer: Io,min = 0.09545 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 10.5/15 = 0.7
Ripple current
ΔIL = 10.5·0.3/(330·10⁻⁶·50·10³) = 0.1909 A
Boundary load current
Io,min = ΔIL/2 = 0.09545 A
Answer
Io,min = 0.09545 A
Below this current the converter enters discontinuous conduction and Vo rises above D·Vin.
11.Wheatstone bridge & strain gauges
Answer: Pg = 125 mW
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Voltage across the gauge
V = 10/2 = 5 V
Power
Pg = 5²/200 = 125 mW
Answer
Pg = 125 mW
12.Wheatstone bridge & strain gauges
Answer: σ = 28 MPa
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Strain
ε = 4·0.002/(10·2) = 0.0004
Stress
σ = 70·10³ MPa·0.0004 = 28 MPa
Answer
σ = 28 MPa
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 5
Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.
Output expression
F = A′B′ + A′BC + AB′C + ABC
Rows with F = 1
ABC = 000, 001, 011, 101, 111
N = 5
Answer
N = 5
14.Digital logic: gates, K-maps & flip-flops
Answer: N = 4
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Prime implicants
The largest groups that can be formed from 1s and Xs.