Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 150 has voltage-divider bias from VCC = 12 V: R₁ = 56 kΩ from VCC to the base and R₂ = 10 kΩ from the base to ground. The collector resistor is RC = 3.3 kΩ and the emitter resistor is RE = 2.2 kΩ. Take VBE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector current IC in mA.
A 5.1 V Zener regulator has a 100 Ω series resistor. The input can rise to 21 V, and the load may be disconnected. Find the largest power PZ,max the Zener must dissipate.
Vin,max = 21 VVZ = 5.1 VR = 100 Ω
PZ,max = mW
3.Op-amp circuitsMedium
The difference amplifier uses an ideal op-amp with ±15 V supplies, with R3 = R1 and R4 = R2. Find the output voltage Vout.
V1 = 0.7 VV2 = 0.1 VR1 = R3 = 2 kΩR2 = R4 = 22 kΩ
Vout = V
4.Op-amp circuitsHard
The integrator uses an ideal op-amp with ±15 V supplies; its output saturates at ±13 V. The capacitor is uncharged when a constant input Vin = 2.7 V is applied at t = 0. Find the output voltage Vout at t = 5 ms.
The inductor carries no current before the switch closes at t = 0. How long after the switch closes does the current reach 90% of its final value? Find t.
Vs = 10 VR = 10 ΩL = 22 mH
t = ms
6.RC & RL transientsHard
The switch across R2 has been open for a long time, so the inductor current is steady. At t = 0 the switch closes and shorts out R2. Find the inductor current i at t = 1 ms.
Vs = 12 VR1 = 47 ΩR2 = 33 ΩL = 33 mHt = 1 ms
i = A
7.Series & parallel resistorsMedium
Find the equivalent resistance Req seen by the source V1.
A buck converter turns 12 V into 9 V for a 12 Ω load. It switches at 40 kHz with L = 100 µH. Find the peak inductor current Imax.
Vin = 12 VVo = 9 Vf = 40 kHzL = 100 µHR = 12 Ω
Imax = A
10.DC-DC convertersHard
An ideal buck-boost converter turns 36 V into −108 V for a 10 Ω load at 20 kHz. The output capacitor is 220 µF. Find the peak-to-peak output voltage ripple ΔVo in mV.
A bridge with four 100 Ω arms is supplied with 9 V. When the sensor R₂ changes, the output reads Vab = 173.1 mV. Find the exact change ΔR of R₂.
Vs = 9 VR = 100 ΩVab = 173.1 mV
ΔR = Ω
12.Wheatstone bridge & strain gaugesHard
A load cell (a full bridge of strain gauges) has a rated output of 3 mV/V at its rated load of 200 kg. It is excited with 12 V. Find its output Vo under a load of 160 kg.
Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C) = Σm(2, 3, 4, 6, 7). How many literals L does it contain in total (a primed variable counts as one literal)?
F(A, B, C) = Σm(2, 3, 4, 6, 7)
L =
14.Digital logic: gates, K-maps & flip-flopsHard
A 5-bit ripple (asynchronous) counter is built from flip-flops with a propagation delay of 10 ns each. All outputs must have settled before the next clock edge. Find the maximum clock frequency fmax.
n = 5tpd = 10 ns
fmax = MHz
3Solutions
1.Diodes & transistors
Answer: IC = 0.4923 mA
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Thévenin equivalent of the divider
VTH = 12·10/(56 + 10) = 1.818 V
RTH = 56·10/(56 + 10) = 8.485 kΩ
Base current
KVL around the base loop; the emitter current is (β + 1)·IB.
IB = (1.818 − 0.7)/(8.485 + 151·2.2) = 3.282 µA
Collector current
IC = 150·3.282 µA = 0.4923 mA
IE = 151·3.282 µA = 0.4956 mA
Answer
IC = 0.4923 mA
2.Diodes & transistors
Answer: PZ,max = 810.9 mW
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Worst-case Zener current
IZ = 15.9/100 = 159 mA
Zener power
PZ = 5.1·159 = 810.9 mW
Answer
PZ,max = 810.9 mW
3.Op-amp circuits
Answer: Vout = −6.6 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Voltage at the inputs
R₃ and R₄ carry the same current, so they form a voltage divider; feedback makes V₋ = V₊.
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Input current and ramp rate
kΩ times µF gives milliseconds.
RC = 2.2 kΩ · 2.2 µF = 4.84 ms
ramp rate = −Vin/(RC) = −2.7/4.84 = −0.5579 V/ms
Output at the given time
The ideal value lies inside ±Vsat, so the integrator has not clipped yet.
Vout = −Vin·t/(RC) = −2.7·5/4.84 = −2.789 V
Answer
Vout = −2.789 V
5.RC & RL transients
Answer: t = 5.066 ms
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
τ = L/R = 22 mH / 10 Ω = 2.2 ms
i(∞) = Vs/R = 10/10 = 1 A
Solve for the time
0.9 = 1 − e−t/τ → t = −τ·ln(1 − 0.9)
t = −2.2·ln(0.1) = 5.066 ms
Answer
t = 5.066 ms
6.RC & RL transients
Answer: i = 0.23 A
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial value, final value, time constant
Before t = 0 both resistors are in the loop; afterwards the closed switch bypasses R₂.
i(0) = 12/(47 + 33) = 0.15 A
i(∞) = 12/47 = 0.2553 A
τ = L/R = 33/47 = 0.7021 ms
i(t) = 0.2553 + (0.15 − 0.2553)·e−t/τ
Current at the given time
i(1) = 0.2553 + (−0.1053)·e−1/0.7021 = 0.23 A
Answer
i = 0.23 A
7.Series & parallel resistors
Answer: Req = 17.55 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 12 + 5 = 17 Ω
R2 ∥ 17 = 3·17/(3+17) = 2.55 Ω
Req = R1 + 2.55 = 15 + 2.55 = 17.55 Ω
Answer
Req = 17.55 Ω
8.Series & parallel resistors
Answer: IR2 = 1.816 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 5 + 20 = 25 Ω
R4 ∥ 25 = 9.375 Ω
R3 + 9.375 = 11.38 Ω
R2 ∥ 11.38 = 4.697 Ω
Req = R1 + 4.697 = 5 + 4.697 = 9.697 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 30/9.697 = 3.094 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 30 − 3.094·5 = 14.53 V
IR2 = VA/R2 = 14.53/8 = 1.816 A
Answer
IR2 = 1.816 A
9.DC-DC converters
Answer: Imax = 1.031 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 9/12 = 0.75
Average and ripple current
Io = 9/12 = 0.75 A
ΔIL = VL·D/(L·f) = 3·0.75/(100·10⁻⁶·40·10³) = 0.5625 A
Peak current
Imax = 0.75 + 0.5625/2 = 1.031 A
Answer
Imax = 1.031 A
10.DC-DC converters
Answer: ΔVo = 1841 mV
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 108/(36 + 108) = 0.75
Load current
Io = 108/10 = 10.8 A
Output ripple
ΔVo = 10.8·0.75/(20·10³·220·10⁻⁶) = 1841 mV
Answer
ΔVo = 1841 mV
11.Wheatstone bridge & strain gauges
Answer: ΔR = 8 Ω
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Node voltage
Va = 4.5 + 0.1731 = 4.673 V
Solve the divider
R₂ = 100·4.673/(9 − 4.673) = 108 Ω
ΔR = 108 − 100 = 8 Ω
Answer
ΔR = 8 Ω
12.Wheatstone bridge & strain gauges
Answer: Vo = 28.8 mV
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Full-scale output
3·12 = 36 mV
Output at this load
Vo = 36·160/200 = 28.8 mV
Answer
Vo = 28.8 mV
13.Digital logic: gates, K-maps & flip-flops
Answer: L = 3
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Group the 1s
Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.
B
AC′
Minimal SOP form
F = B + AC′
L = 3
Answer
L = 3
14.Digital logic: gates, K-maps & flip-flops
Answer: fmax = 20 MHz
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.