Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

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1Formulas and methods

Diodes & transistors

Diode (constant drop)
VD = 0.7 V when conducting
Active region
VBE = 0.7 V, IC = β·IB, IE = (β + 1)·IB
Fixed bias
IB = (VCC − 0.7)/RB
Divider bias
IB = (VTH − 0.7)/(RTH + (β + 1)RE)
Thévenin of the divider
VTH = VCC·R2/(R1 + R2), RTH = R1∥R2
Collector loop
VCE = VCC − ICRC − IERE
Saturation
IC(sat) = (VCC − VCE(sat))/RC, IB ≥ IC(sat)/β

Op-amp circuits

Inverting amplifier
Vout = −(Rf/Rin)·Vin
Non-inverting amplifier
Vout = (1 + Rf/R1)·Vin
Summing amplifier
Vout = −Rf(V1/R1 + V2/R2)
Ideal op-amp
V+ = V−, Iin = 0

RC & RL transients

Time constant
τ = RC | τ = L/R
Response
x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ
Capacitor at DC
open circuit; vC cannot jump
Inductor at DC
short circuit; iL cannot jump
Settled
t ≈ 5τ

Method

  1. Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
  2. Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
  3. Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
  4. Use x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ.

Series & parallel resistors

Resistors in series
Req = R1 + R2 + …
Resistors in parallel
1/Req = 1/R1 + 1/R2 + …
Two in parallel
Req = R1R2 / (R1 + R2)
Ohm's law
V = I·R
Power
P = V·I = I²R = V²/R

Method

  1. Start at the end of the network furthest from the terminals.
  2. Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
  3. Redraw the circuit after each step.
  4. Repeat until one resistor is left between the terminals.

DC-DC converters

Buck
Vo = D·Vin
Boost
Vo = Vin/(1 − D)
Inverting buck-boost
|Vo| = Vin·D/(1 − D)
Ideal power balance
VinIin = VoIo
Inductor ripple
ΔIL = VL,on·D/(L·f); buck Vin − Vo, boost and buck-boost Vin
Average inductor current
buck Io; boost and buck-boost Io/(1 − D)
Output ripple
buck ΔIL/(8fC); boost and buck-boost Io·D/(fC)
CCM boundary
buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

  1. Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
  2. Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
  3. Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
  4. For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.

Wheatstone bridge & strain gauges

Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε

Method

  1. Treat the bridge as two voltage dividers across the same supply.
  2. For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
  3. For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
  4. For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium
RC​ = 1 kΩβ = 150VCC​ = 10 VRB​ = 220 kΩ

An NPN transistor with β = 150 is biased by a base resistor RB = 220 kΩ from the supply VCC = 10 V. The collector resistor is RC = 1 kΩ and the emitter is grounded. Take VBE = 0.7 V and assume the transistor is in the active region. Find the collector–emitter voltage VCE.

VCC = 10 VRB = 220 kΩRC = 1 kΩβ = 150VBE = 0.7 V
VCE = V
2.Diodes & transistorsHard
RC​ = 680 Ωβ = 200VCC​ = 24 V5 VRB​ = ?

An NPN transistor with β = 200 switches a 680 Ω load resistor connected between VCC = 24 V and its collector. The emitter is grounded. The base is driven from a 5 V logic output through a base resistor RB. Take VBE = 0.7 V and VCE(sat) = 0.2 V. For reliable switching, design for a base current 2 times the minimum needed for saturation. Find RB in kΩ.

VCC = 24 VRC = 680 Ωβ = 200Vin = 5 VVBE = 0.7 VVCE(sat) = 0.2 Voverdrive = 2
RB = kΩ
3.Op-amp circuitsMedium
−+Vout​R2​ = 2 kΩV1​ = −1.9 VR1​ = 1 kΩV2​ = −1.2 VR3​ = 1 kΩR4​ = 2 kΩ

The difference amplifier uses an ideal op-amp with ±15 V supplies, with R3 = R1 and R4 = R2. Find the output voltage Vout.

V1 = −1.9 VV2 = −1.2 VR1 = R3 = 1 kΩR2 = R4 = 2 kΩ
Vout = V
4.Op-amp circuitsHard
Vin​V1​Vout​stage 1: invertingR1​ = 4.7 kΩRf1​ = 47 kΩstage 2: non-invertingR2​ = 100 kΩRf2​ = 100 kΩ

Two ideal op-amp stages are connected in cascade: an inverting amplifier (R1, Rf1) followed by a non-inverting amplifier (R2 to ground, Rf2 in the feedback). Both run from ±15 V supplies. The input is Vin = −0.4 V. Find the output voltage Vout.

R1 = 4.7 kΩRf1 = 47 kΩR2 = 100 kΩRf2 = 100 kΩVin = −0.4 V
Vout = V
5.RC & RL transientsMedium
R = 33 Ωt = 0L33 mHi(t)

The inductor carries a steady current of 1.5 A. At t = 0 the switch closes the loop through R and the source is removed, so the inductor current decays through R. Find the current i at t = 1 ms.

i(0) = 1.5 AR = 33 ΩL = 33 mHt = 1 ms
i = A
6.RC & RL transientsHard
+−Vs​15 Vt = 0R = 6.8 kΩC22 µF+−vC​vC​(0) = 30 V

Just before the switch closes at t = 0, the capacitor holds 30 V with the polarity shown. How long does it take for vC to reach 22.5 V? Find t.

Vs = 15 VR = 6.8 kΩC = 22 µFvC(0) = 30 V
t = ms
7.Series & parallel resistorsMedium
R1​ = 10 ΩR3​ = 8 Ω+−V1​12 VR2​8 ΩIR2​AR4​6 ΩB

Find the current IR2 through R2.

V1 = 12 VR1 = 10 ΩR2 = 8 ΩR3 = 8 ΩR4 = 6 Ω
IR2 = A
8.Series & parallel resistorsHard
R1​ = 6 ΩIR1​R3​ = 2 ΩR5​ = 10 Ω+−V1​10 VR2​8 ΩAR4​4 ΩBR6​6 Ω

Find the current IR1 delivered by the source, which flows through R1.

V1 = 10 VR1 = 6 ΩR2 = 8 ΩR3 = 2 ΩR4 = 4 ΩR5 = 10 ΩR6 = 6 Ω
IR1 = A
9.DC-DC convertersMedium
+−9 VLSCR = 25 Ω+−36 V

An ideal boost converter turns 9 V into 36 V for a 25 Ω load. Find the average inductor current IL.

Vin​ = 9 VVo​ = 36 VR = 25 Ω
IL = A
10.DC-DC convertersHard
tiL​Imax​IL​DTT2T

An ideal boost converter turns 48 V into 120 V for a 50 Ω load at 200 kHz. Find the smallest inductance Lcrit for continuous conduction.

Vin​ = 48 VVo​ = 120 Vf = 200 kHzR = 50 Ω
Lcrit = µH
11.Wheatstone bridge & strain gaugesMedium
+−6 V500 Ω500 Ω500 Ω500 Ωab+−

A 500 Ω strain gauge is one arm (R₂) of a bridge with four equal 500 Ω arms and an excitation of 6 V. Find the power Pg dissipated in the gauge, in mW. Self-heating limits the excitation.

Vs = 6 VR = 500 Ω
Pg = mW
12.Wheatstone bridge & strain gaugesHard
+−5 V120 Ω − ΔR120 Ω + ΔR120 Ω120 Ωab+−Vo​ = ?

A bridge with 120 Ω arms is excited with 5 V and has two active gauges in adjacent arms, one in tension and one in compression (half bridge). The gauge factor is 2.1 and the strain is 800 µε. Find the bridge output Vo in mV.

Vs = 5 VGF = 2.1ε = 800 µε
Vo = mV
13.Digital logic: gates, K-maps & flip-flopsMedium
ABC00011110011011030204151706

Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C) = Σm(0, 1, 5, 7). How many literals L does it contain in total (a primed variable counts as one literal)?

F(A, B, C) = Σm(0, 1, 5, 7)
L =
14.Digital logic: gates, K-maps & flip-flopsHard
ABCD0001111000011110001103X204051716X12X130151140809011X10

For F(A, B, C, D) = Σm(1, 6, 7, 14) + d(2, 10, 12, 13), where d marks the don't-care conditions, find the number N of essential prime implicants.

F(A, B, C, D) = Σm(1, 6, 7, 14) + d(2, 10, 12, 13)
N =

3Solutions

1.Diodes & transistors

Answer: VCE = 3.659 V

BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.

Base current

IB = (VCC − VBE)/RB = (10 − 0.7)/220 kΩ = 42.27 µA

Collector current

IC = β·IB = 150·42.27 µA = 6.341 mA

Collector–emitter voltage

VCE = 10 − 6.341 mA·1 kΩ = 3.659 V

Answer

VCE = 3.659 V
2.Diodes & transistors

Answer: RB = 12.29 kΩ

BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.

Collector current in saturation

IC(sat) = (24 − 0.2)/680 = 35 mA

Minimum base current

IB(min) = IC(sat)/β = 35/200 = 175 µA

Design base current

IB = 2·175 µA = 350 µA

Base resistor

RB = (5 − 0.7)/IB = 4.3 V/0.35 mA = 12.29 kΩ

Answer

RB = 12.29 kΩ
3.Op-amp circuits

Answer: Vout = 1.4 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Voltage at the inputs

R₃ and R₄ carry the same current, so they form a voltage divider; feedback makes V₋ = V₊.

V₊ = V2·R4/(R3 + R4) = −1.2·2/(1 + 2) = −0.8 V
V₋ = V₊

KCL at the inverting input

(−1.9 − −0.8)/1 = (−0.8 − Vout)/2
Vout = (R2/R1)·(V2 − V1) = (2/1)·(−1.2 − (−1.9)) = 1.4 V

Answer

Vout = 1.4 V
4.Op-amp circuits

Answer: Vout = 8 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Gain of each stage

A1 = −Rf1/R1 = −47/4.7 = −10
A2 = 1 + Rf2/R2 = 1 + 100/100 = 2

Stage by stage

V1 = −10·(−0.4) = 4 V
Vout = 2·4 = 8 V

Answer

Vout = 8 V
5.RC & RL transients

Answer: i = 0.5518 A

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Time constant

τ = L/R = 33 mH / 33 Ω = 1 ms

Decay of the current

i(t) = 1.5·e−1/1 = 0.5518 A

Answer

i = 0.5518 A
6.RC & RL transients

Answer: t = 103.7 ms

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Initial value, final value, time constant

The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.

vC(0) = 30 V, vC(∞) = Vs = 15 V
τ = R·C = 6.8 kΩ · 22 µF = 149.6 ms
vC(t) = 15 + (30 − 15)·e−t/τ

Solve for the time

22.5 = 15 + (15)·e−t/τ → e−t/τ = (22.5 − 15)/(30 − 15) = 0.5
t = τ·ln((30 − 15)/(22.5 − 15)) = 149.6·ln(2) = 103.7 ms

Answer

t = 103.7 ms
7.Series & parallel resistors

Answer: IR2 = 0.506 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 10 ΩR3​ = 8 Ω+−V1​12 VR2​8 ΩAR4​6 ΩB

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R3 + R4 = 8 + 6 = 14 Ω
R2 ∥ 14 = 8·14/(8+14) = 5.091 Ω
Req = R1 + 5.091 = 10 + 5.091 = 15.09 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 12/15.09 = 0.7952 A

Current through R₂

Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.

VA = V1 − IR1·R1 = 12 − 0.7952·10 = 4.048 V
IR2 = VA/R2 = 4.048/8 = 0.506 A

Answer

IR2 = 0.506 A
8.Series & parallel resistors

Answer: IR1 = 1.093 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 6 ΩR3​ = 2 ΩR5​ = 10 Ω+−V1​10 VR2​8 ΩAR4​4 ΩBR6​6 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R5 + R6 = 10 + 6 = 16 Ω
R4 ∥ 16 = 3.2 Ω
R3 + 3.2 = 5.2 Ω
R2 ∥ 5.2 = 3.152 Ω
Req = R1 + 3.152 = 6 + 3.152 = 9.152 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 10/9.152 = 1.093 A

Answer

IR1 = 1.093 A
9.DC-DC converters

Answer: IL = 5.76 A

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 1 − 9/36 = 0.75

Load current

Io = 36/25 = 1.44 A

Inductor current

IL = Io/(1 − D) = 1.44/0.25 = 5.76 A

Answer

IL = 5.76 A
10.DC-DC converters

Answer: Lcrit = 12 µH

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 1 − 48/120 = 0.6

Boundary condition

Set the average inductor current equal to half the ripple current and solve for L.

Lcrit = D(1 − D)²·R/(2f)

Critical inductance

Lcrit = 0.6(1 − 0.6)²·50/(2200·10³) = 12 µH

Answer

Lcrit = 12 µH
11.Wheatstone bridge & strain gauges

Answer: Pg = 18 mW

Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.

Voltage across the gauge

V = 6/2 = 3 V

Power

Pg = 3²/500 = 18 mW

Answer

Pg = 18 mW
12.Wheatstone bridge & strain gauges

Answer: Vo = 4.2 mV

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Relative resistance change

ΔR/R = 2.1·800·10⁻⁶ = 0.00168

Bridge output

Vo = Vs·GF·ε/2 = 5·0.00168/2 = 4.2 mV

Answer

Vo = 4.2 mV
13.Digital logic: gates, K-maps & flip-flops

Answer: L = 4

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

ABC00011110011011030204151706

Group the 1s

Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.

AC
A′B′

Minimal SOP form

F = AC + A′B′
L = 4

Answer

L = 4
14.Digital logic: gates, K-maps & flip-flops

Answer: N = 2

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Prime implicants

The largest groups that can be formed from 1s and Xs.

CD′, ABD′, A′BC, A′B′C′D
ABCD0001111000011110001103X204051716X12X130151140809011X10

Essential prime implicants

A′BC, A′B′C′D
N = 2

Answer

N = 2

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