Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 150 is biased by a base resistor RB = 470 kΩ from the supply VCC = 10 V. The collector resistor is RC = 470 Ω and the emitter is grounded. Take VBE = 0.7 V and assume the transistor is in the active region. Find the collector–emitter voltage VCE.
VCC = 10 VRB = 470 kΩRC = 470 Ωβ = 150VBE = 0.7 V
VCE = V
2.Diodes & transistorsHard
An NPN transistor with β = 80 switches a 220 Ω load resistor connected between VCC = 24 V and its collector. The emitter is grounded. The base is driven from a 5 V logic output through a base resistor RB = 4.7 kΩ. Take VBE = 0.7 V and VCE(sat) = 0.2 V. Find the collector current IC in mA when the input is high. Decide first whether the transistor is saturated.
Choose the feedback resistor Rf that gives this non-inverting amplifier a voltage gain of 8.
R1 = 2 kΩAv = 8
Rf = kΩ
4.Op-amp circuitsHard
Two ideal op-amp stages are connected in cascade: an inverting amplifier (R1, Rf1) followed by a non-inverting amplifier (R2 to ground, Rf2 in the feedback). Both run from ±15 V supplies. The input is Vin = −0.05 V. Find the output voltage Vout.
The inductor carries no current before the switch closes at t = 0. Find the voltage vL across the inductor at t = 1 ms.
Vs = 12 VR = 50 ΩL = 33 mHt = 1 ms
vL = V
6.RC & RL transientsHard
The switch across R2 has been open for a long time, so the inductor current is steady. At t = 0 the switch closes and shorts out R2. Find the inductor current i at t = 5 ms.
Vs = 6 VR1 = 15 ΩR2 = 20 ΩL = 47 mHt = 5 ms
i = A
7.Series & parallel resistorsMedium
Find the equivalent resistance Req seen by the source V1.
V1 = 18 VR1 = 6 ΩR2 = 12 ΩR3 = 5 ΩR4 = 6 Ω
Req = Ω
8.Series & parallel resistorsHard
Find the equivalent resistance Req seen by the source V1.
An ideal boost converter turns 48 V into 64 V at 50 kHz with L = 330 µH. Find the peak-to-peak inductor ripple current ΔIL.
Vin = 48 VVo = 64 Vf = 50 kHzL = 330 µH
ΔIL = A
10.DC-DC convertersHard
An ideal buck-boost converter turns 36 V into −36 V for a 2 Ω load at 50 kHz. The output capacitor is 470 µF. Find the peak-to-peak output voltage ripple ΔVo in mV.
Vin = 36 VVo = −36 Vf = 50 kHzC = 470 µFR = 2 Ω
ΔVo = mV
11.Wheatstone bridge & strain gaugesMedium
Find the Thévenin resistance Rth of the bridge shown, seen from the output terminals a and b.
Vs = 10 VR1 = 20 ΩR2 = 1000 ΩR3 = 100 ΩR4 = 60 Ω
Rth = Ω
12.Wheatstone bridge & strain gaugesHard
A quarter bridge with one active gauge (GF = 2.12) is excited with 3 V. Under load the output reads 1.193 mV. Find the strain ε in µε.
In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.
F = Σm(1, 5, 6, 7, 8)
1AB = 00, CD = 00
2AB = 00, CD = 01
3AB = 00, CD = 11
4AB = 00, CD = 10
5AB = 01, CD = 00
6AB = 01, CD = 01
7AB = 01, CD = 11
8AB = 01, CD = 10
9AB = 11, CD = 00
10AB = 11, CD = 01
11AB = 11, CD = 11
12AB = 11, CD = 10
13AB = 10, CD = 00
14AB = 10, CD = 01
15AB = 10, CD = 11
16AB = 10, CD = 10
14.Digital logic: gates, K-maps & flip-flopsHard
A 4-bit binary down counter starts at 14 (decimal, Q = 1110). Which count Q (in decimal) does it show after 21 clock pulses?
Q0 = 1421n = 4
Q =
3Solutions
1.Diodes & transistors
Answer: VCE = 8.605 V
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.
Base current
IB = (5 − 0.7)/4.7 kΩ = 914.9 µA
Saturated or active?
β·IB is smaller than IC(sat), so the transistor stays active.
β·IB = 73.19 mA
IC(sat) = (24 − 0.2)/220 = 108.2 mA
Collector current
IC = β·IB = 73.19 mA
Answer
IC = 73.19 mA
The transistor is active, so the load is not fully switched on.
3.Op-amp circuits
Answer: Rf = 14 kΩ
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain of a non-inverting amplifier
V₋ = V₊ = Vin, and the current through R₁ also flows through Rf, so Vout = Vin·(1 + Rf/R₁).
Av = 1 + Rf/R1
Rf = (8 − 1)·2 = 14 kΩ
Answer
Rf = 14 kΩ
4.Op-amp circuits
Answer: Vout = 1 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain of each stage
A1 = −Rf1/R1 = −47/4.7 = −10
A2 = 1 + Rf2/R2 = 1 + 47/47 = 2
Stage by stage
V1 = −10·(−0.05) = 0.5 V
Vout = 2·0.5 = 1 V
Answer
Vout = 1 V
5.RC & RL transients
Answer: vL = 2.637 V
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
τ = L/R = 33 mH / 50 Ω = 0.66 ms
i(∞) = Vs/R = 12/50 = 0.24 A
Inductor voltage
At t = 0 the whole supply voltage appears across the inductor; it then decays to zero.
vL(t) = Vs·e−t/τ = 12·e−1/0.66 = 2.637 V
Answer
vL = 2.637 V
6.RC & RL transients
Answer: i = 0.3537 A
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial value, final value, time constant
Before t = 0 both resistors are in the loop; afterwards the closed switch bypasses R₂.
i(0) = 6/(15 + 20) = 0.1714 A
i(∞) = 6/15 = 0.4 A
τ = L/R = 47/15 = 3.133 ms
i(t) = 0.4 + (0.1714 − 0.4)·e−t/τ
Current at the given time
i(5) = 0.4 + (−0.2286)·e−5/3.133 = 0.3537 A
Answer
i = 0.3537 A
7.Series & parallel resistors
Answer: Req = 11.74 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 5 + 6 = 11 Ω
R2 ∥ 11 = 12·11/(12+11) = 5.739 Ω
Req = R1 + 5.739 = 6 + 5.739 = 11.74 Ω
Answer
Req = 11.74 Ω
8.Series & parallel resistors
Answer: Req = 14.94 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 4 + 4 = 8 Ω
R4 ∥ 8 = 4.444 Ω
R3 + 4.444 = 19.44 Ω
R2 ∥ 19.44 = 10.94 Ω
Req = R1 + 10.94 = 4 + 10.94 = 14.94 Ω
Answer
Req = 14.94 Ω
9.DC-DC converters
Answer: ΔIL = 0.7273 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 1 − 48/64 = 0.25
Inductor voltage during the on-time
While S is on, the inductor sits directly across Vin.
VL = 48 V
Ripple current
ΔIL = VL·D/(L·f) = 48·0.25/(330·10⁻⁶·50·10³) = 0.7273 A
Answer
ΔIL = 0.7273 A
10.DC-DC converters
Answer: ΔVo = 383 mV
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 36/(36 + 36) = 0.5
Load current
Io = 36/2 = 18 A
Output ripple
ΔVo = 18·0.5/(50·10³·470·10⁻⁶) = 383 mV
Answer
ΔVo = 383 mV
11.Wheatstone bridge & strain gauges
Answer: Rth = 57.11 Ω
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Supply shorted
R₁∥R₂ = 20·1000/1020 = 19.61 Ω
R₃∥R₄ = 100·60/160 = 37.5 Ω
Thévenin resistance
Rth = 57.11 Ω
Answer
Rth = 57.11 Ω
12.Wheatstone bridge & strain gauges
Answer: ε = 750.3 µε
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Solve the quarter-bridge equation
ε = 4·0.001193/(3·2.12) = 0.0007503
In microstrain
ε = 750.3 µε
Answer
ε = 750.3 µε
13.Digital logic: gates, K-maps & flip-flops
Answer: AB = 10, CD = 00
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Neighbours of each 1
A 1 with a neighbouring 1 can join a group of two or more.
m8: m9, m10, m12, m0 → 0
The isolated 1
m8 = AB′C′D′ → AB = 10, CD = 00
Answer
AB = 10, CD = 00
14.Digital logic: gates, K-maps & flip-flops
Answer: Q = 9
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
Full cycles
Every 16 pulses bring the counter back to the same state.