Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

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1Formulas and methods

Diodes & transistors

Diode (constant drop)
VD = 0.7 V when conducting
Active region
VBE = 0.7 V, IC = β·IB, IE = (β + 1)·IB
Fixed bias
IB = (VCC − 0.7)/RB
Divider bias
IB = (VTH − 0.7)/(RTH + (β + 1)RE)
Thévenin of the divider
VTH = VCC·R2/(R1 + R2), RTH = R1∥R2
Collector loop
VCE = VCC − ICRC − IERE
Saturation
IC(sat) = (VCC − VCE(sat))/RC, IB ≥ IC(sat)/β

Op-amp circuits

Inverting amplifier
Vout = −(Rf/Rin)·Vin
Non-inverting amplifier
Vout = (1 + Rf/R1)·Vin
Summing amplifier
Vout = −Rf(V1/R1 + V2/R2)
Ideal op-amp
V+ = V−, Iin = 0

RC & RL transients

Time constant
τ = RC | τ = L/R
Response
x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ
Capacitor at DC
open circuit; vC cannot jump
Inductor at DC
short circuit; iL cannot jump
Settled
t ≈ 5τ

Method

  1. Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
  2. Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
  3. Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
  4. Use x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ.

Series & parallel resistors

Resistors in series
Req = R1 + R2 + …
Resistors in parallel
1/Req = 1/R1 + 1/R2 + …
Two in parallel
Req = R1R2 / (R1 + R2)
Ohm's law
V = I·R
Power
P = V·I = I²R = V²/R

Method

  1. Start at the end of the network furthest from the terminals.
  2. Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
  3. Redraw the circuit after each step.
  4. Repeat until one resistor is left between the terminals.

DC-DC converters

Buck
Vo = D·Vin
Boost
Vo = Vin/(1 − D)
Inverting buck-boost
|Vo| = Vin·D/(1 − D)
Ideal power balance
VinIin = VoIo
Inductor ripple
ΔIL = VL,on·D/(L·f); buck Vin − Vo, boost and buck-boost Vin
Average inductor current
buck Io; boost and buck-boost Io/(1 − D)
Output ripple
buck ΔIL/(8fC); boost and buck-boost Io·D/(fC)
CCM boundary
buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

  1. Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
  2. Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
  3. Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
  4. For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.

Wheatstone bridge & strain gauges

Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε

Method

  1. Treat the bridge as two voltage dividers across the same supply.
  2. For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
  3. For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
  4. For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium
RC​ = 470 Ωβ = 50IC​ = ?VCC​ = 12 VRB​ = 220 kΩ

An NPN transistor with β = 50 is biased by a base resistor RB = 220 kΩ from the supply VCC = 12 V. The collector resistor is RC = 470 Ω and the emitter is grounded. Take VBE = 0.7 V and assume the transistor is in the active region. Find the collector current IC in mA.

VCC = 12 VRB = 220 kΩRC = 470 Ωβ = 50VBE = 0.7 V
IC = mA
2.Diodes & transistorsHard
+−≤ 21 V100 Ω6.2 V

A 6.2 V Zener regulator has a 100 Ω series resistor. The input can rise to 21 V, and the load may be disconnected. Find the largest power PZ,max the Zener must dissipate.

Vin,max = 21 VVZ = 6.2 VR = 100 Ω
PZ,max = mW
3.Op-amp circuitsMedium
−+Vout​Rf​ = 100 kΩR1​ = 100 kΩVin​ = 0.9 V

The op-amp is ideal and runs from ±15 V supplies. Find the output voltage Vout.

Vin = 0.9 VR1 = 100 kΩRf = 100 kΩ
Vout = V
4.Op-amp circuitsHard
−+Vout​Rf​ = 1 kΩV1​ = 0.7 VR1​ = 47 kΩV2​ = −1.8 VR2​ = 2 kΩIf​

The summing amplifier uses an ideal op-amp with ±15 V supplies. Find the current If through the feedback resistor, flowing towards the output.

V1 = 0.7 VV2 = −1.8 VR1 = 47 kΩR2 = 2 kΩRf = 1 kΩ
If = mA
5.RC & RL transientsMedium
+−Vs​12 Vt = 0R = 20 ΩL10 mHi(t)

The inductor carries no current before the switch closes at t = 0. Find the energy W(∞) stored in the inductor once the circuit has settled, in mJ.

Vs = 12 VR = 20 ΩL = 10 mH
W(∞) = mJ
6.RC & RL transientsHard
+−Vs​5 Vt = 0R = 1 kΩC?+−vC​

A timer starts charging an uncharged capacitor through a resistor from a 5 V supply at t = 0. It must trigger when the capacitor voltage reaches 4 V, exactly 25 ms after the start. With R = 1 kΩ, find the capacitance C needed.

Vs = 5 VVth = 4 VT = 25 msR = 1 kΩ
C = µF
7.Series & parallel resistorsMedium
R1​ = 3 ΩR3​ = 2 Ω+−V1​18 VR2​10 ΩIR2​AR4​12 ΩB

Find the current IR2 through R2.

V1 = 18 VR1 = 3 ΩR2 = 10 ΩR3 = 2 ΩR4 = 12 Ω
IR2 = A
8.Series & parallel resistorsHard
R1​ = 12 ΩR3​ = 5 ΩR5​ = 30 Ω+−V1​30 VR2​30 ΩIR2​AR4​5 ΩBR6​12 Ω

Find the current IR2 through R2.

V1 = 30 VR1 = 12 ΩR2 = 30 ΩR3 = 5 ΩR4 = 5 ΩR5 = 30 ΩR6 = 12 Ω
IR2 = A
9.DC-DC convertersMedium
tiL​Imax​Imin​ΔI = ?DTT2T

An ideal buck converter turns 12 V into 6 V at 200 kHz with L = 10 µH. Find the peak-to-peak inductor ripple current ΔIL.

Vin​ = 12 VVo​ = 6 Vf = 200 kHzL = 10 µH
ΔIL = A
10.DC-DC convertersHard
+−9 VSL = 47 µHC = ?R+−6.3 V

A buck converter turns 9 V into 6.3 V at 500 kHz with L = 47 µH. Find the output capacitance C that limits the peak-to-peak output ripple to 5 mV.

Vin​ = 9 VVo​ = 6.3 Vf = 500 kHzL = 47 µHΔVo = 5 mV
C = µF
11.Wheatstone bridge & strain gaugesMedium
+−6 V400 Ω400 Ω + ΔR400 Ω400 Ωab+−Vab​ = ?

A bridge has four 400 Ω arms and Vs = 6 V. The sensor R₂ increases by ΔR = 20 Ω. Find the exact output Vab in mV.

Vs = 6 VR = 400 ΩΔR = 20 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
+−V120 Ω120 Ω + ΔR120 Ω120 Ωab+−

A 120 Ω strain gauge with gauge factor 2.1 is bonded to a steel bar. Under load its resistance rises by 0.1008 Ω. Find the strain ε in microstrain (µε).

R = 120 ΩGF = 2.1ΔR = 0.1008 Ω
ε = µε
13.Digital logic: gates, K-maps & flip-flopsMedium
ABCD00011110000111101111111

In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.

F = Σm(1, 5, 7, 11, 12, 13, 14)
  1. 1AB = 00, CD = 00
  2. 2AB = 00, CD = 01
  3. 3AB = 00, CD = 11
  4. 4AB = 00, CD = 10
  5. 5AB = 01, CD = 00
  6. 6AB = 01, CD = 01
  7. 7AB = 01, CD = 11
  8. 8AB = 01, CD = 10
  9. 9AB = 11, CD = 00
  10. 10AB = 11, CD = 01
  11. 11AB = 11, CD = 11
  12. 12AB = 11, CD = 10
  13. 13AB = 10, CD = 00
  14. 14AB = 10, CD = 01
  15. 15AB = 10, CD = 11
  16. 16AB = 10, CD = 10
14.Digital logic: gates, K-maps & flip-flopsHard
DQ3​Q3​DQ2​Q2​DQ1​Q1​DQ0​Q0​CLKRING

A 4-bit ring counter Q₃Q₂Q₁Q₀ starts at 1001. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀) and Q₃ receives Q₀. Give the state Q = Q₃Q₂Q₁Q₀ as a decimal number after 5 clock edges.

Q₃Q₂Q₁Q₀ = 10015
Q =

3Solutions

1.Diodes & transistors

Answer: IC = 2.568 mA

BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.

Base current

IB = (VCC − VBE)/RB = (12 − 0.7)/220 kΩ = 51.36 µA

Collector current

IC = β·IB = 50·51.36 µA = 2.568 mA

Answer

IC = 2.568 mA

Check: VCE = 10.79 V is well above 0.2 V, so the transistor is indeed active.

2.Diodes & transistors

Answer: PZ,max = 917.6 mW

Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.

Worst-case Zener current

IZ = 14.8/100 = 148 mA

Zener power

PZ = 6.2·148 = 917.6 mW

Answer

PZ,max = 917.6 mW
3.Op-amp circuits

Answer: Vout = 1.8 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Inverting input follows the input

V₋ = V₊ = 0.9 V
I = V₋/R1 = 0.9/100 = 0.009 mA

Output voltage

The current through R₁ also flows through Rf.

Vout = V₋ + I·Rf = 0.9 + 0.009·100 = 1.8 V

Answer

Vout = 1.8 V
4.Op-amp circuits

Answer: If = −0.8851 mA

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Input currents

V₋ = 0, so each input resistor has its full input voltage across it.

I1 = V1/R1 = 0.7/47 = 0.01489 mA
I2 = V2/R2 = −1.8/2 = −0.9 mA
If = I1 + I2 = −0.8851 mA

Answer

If = −0.8851 mA
5.RC & RL transients

Answer: W(∞) = 1.8 mJ

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Time constant and final current

Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.

τ = L/R = 10 mH / 20 Ω = 0.5 ms
i(∞) = Vs/R = 12/20 = 0.6 A

Stored energy

W(∞) = ½·L·i(∞)² = ½·10·0.6² = 1.8 mJ

Answer

W(∞) = 1.8 mJ
6.RC & RL transients

Answer: C = 15.53 µF

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Required time constant

4 = 5·(1 − e−25/τ) → τ = 25/ln(5/(5 − 4))
τ = 25/1.609 = 15.53 ms

Capacitance

kΩ times µF gives milliseconds.

C = τ/R = 15.53/1 = 15.53 µF

Answer

C = 15.53 µF
7.Series & parallel resistors

Answer: IR2 = 1.189 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 3 ΩR3​ = 2 Ω+−V1​18 VR2​10 ΩAR4​12 ΩB

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R3 + R4 = 2 + 12 = 14 Ω
R2 ∥ 14 = 10·14/(10+14) = 5.833 Ω
Req = R1 + 5.833 = 3 + 5.833 = 8.833 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 18/8.833 = 2.038 A

Current through R₂

Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.

VA = V1 − IR1·R1 = 18 − 2.038·3 = 11.89 V
IR2 = VA/R2 = 11.89/10 = 1.189 A

Answer

IR2 = 1.189 A
8.Series & parallel resistors

Answer: IR2 = 0.3749 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 12 ΩR3​ = 5 ΩR5​ = 30 Ω+−V1​30 VR2​30 ΩAR4​5 ΩBR6​12 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R5 + R6 = 30 + 12 = 42 Ω
R4 ∥ 42 = 4.468 Ω
R3 + 4.468 = 9.468 Ω
R2 ∥ 9.468 = 7.197 Ω
Req = R1 + 7.197 = 12 + 7.197 = 19.2 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 30/19.2 = 1.563 A

Current through R₂

Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.

VA = V1 − IR1·R1 = 30 − 1.563·12 = 11.25 V
IR2 = VA/R2 = 11.25/30 = 0.3749 A

Answer

IR2 = 0.3749 A
9.DC-DC converters

Answer: ΔIL = 1.5 A

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 6/12 = 0.5

Inductor voltage during the on-time

While S is on, the inductor sits between Vin and Vo.

VL = 12 − 6 = 6 V

Ripple current

ΔIL = VL·D/(L·f) = 6·0.5/(10·10⁻⁶·200·10³) = 1.5 A

Answer

ΔIL = 1.5 A
10.DC-DC converters

Answer: C = 4.021 µF

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 6.3/9 = 0.7

Inductor ripple current

ΔIL = (9 − 6.3)·0.7/(47·10⁻⁶·500·10³) = 0.08043 A

Capacitance

C = 0.08043/(8·500·10³·5·10⁻³) = 4.021 µF

Answer

C = 4.021 µF
11.Wheatstone bridge & strain gauges

Answer: Vab = 73.17 mV

Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.

Node voltages

Va = 6·420/820 = 3.073 V
Vb = 3 V

Output

Vab = 73.17 mV

Answer

Vab = 73.17 mV

The linear estimate Vs·ΔR/(4R) = 75 mV is 2.5 % too high: a quarter bridge is not quite linear.

12.Wheatstone bridge & strain gauges

Answer: ε = 400 µε

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Relative resistance change

ΔR/R = 0.1008/120 = 0.00084

Strain

ε = 0.00084/2.1 = 0.0004 = 400 µε

Answer

ε = 400 µε
13.Digital logic: gates, K-maps & flip-flops

Answer: AB = 10, CD = 11

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Neighbours of each 1

A 1 with a neighbouring 1 can join a group of two or more.

m11: m10, m9, m15, m3 → 0
ABCD00011110000111101111111

The isolated 1

m11 = AB′CD → AB = 10, CD = 11

Answer

AB = 10, CD = 11
14.Digital logic: gates, K-maps & flip-flops

Answer: Q = 12

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

State after every edge

1001 → 1100 → 0110 → 0011 → 1001 → 1100

Decimal value

1100₂ = 12

Answer

Q = 12

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