Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 120 is biased by a base resistor RB = 150 kΩ from the supply VCC = 9 V. The collector resistor is RC = 1.2 kΩ and the emitter is grounded. Take VBE = 0.7 V and assume the transistor is in the active region. Find the collector–emitter voltage VCE.
VCC = 9 VRB = 150 kΩRC = 1.2 kΩβ = 120VBE = 0.7 V
VCE = V
2.Diodes & transistorsHard
An NPN transistor with β = 50 switches a 470 Ω load resistor connected between VCC = 12 V and its collector. The emitter is grounded. The base is driven from a 3.3 V logic output through a base resistor RB = 100 kΩ. Take VBE = 0.7 V and VCE(sat) = 0.2 V. Find the collector current IC in mA when the input is high. Decide first whether the transistor is saturated.
An ideal boost converter turns 36 V into 120 V at 100 kHz with L = 220 µH. Find the peak-to-peak inductor ripple current ΔIL.
Vin = 36 VVo = 120 Vf = 100 kHzL = 220 µH
ΔIL = A
10.DC-DC convertersHard
A buck converter turns 48 V into 19.2 V at 250 kHz with L = 150 µH. Find the output capacitance C that limits the peak-to-peak output ripple to 100 mV.
A galvanometer with a resistance of 50 Ω is connected between a and b of the bridge shown (Vs = 12 V). Find the galvanometer current Ig from a to b, in µA.
A 1000 Ω strain gauge with gauge factor 2.1 is bonded to a steel bar. Under load its resistance rises by 0.42 Ω. Find the strain ε in microstrain (µε).
Use the Karnaugh map to find the minimal product-of-sums (POS) form of F(A, B, C, D) = Σm(2, 5, 8, 9, 10). How many sum terms (factors) N does it have?
F(A, B, C, D) = Σm(2, 5, 8, 9, 10)
N =
14.Digital logic: gates, K-maps & flip-flopsHard
A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown at 8 rising clock edges. How many times N does Q change state?
Q₀ = 0JK
N =
3Solutions
1.Diodes & transistors
Answer: VCE = 1.032 V
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Base current
IB = (VCC − VBE)/RB = (9 − 0.7)/150 kΩ = 55.33 µA
Collector current
IC = β·IB = 120·55.33 µA = 6.64 mA
Collector–emitter voltage
VCE = 9 − 6.64 mA·1.2 kΩ = 1.032 V
Answer
VCE = 1.032 V
2.Diodes & transistors
Answer: IC = 1.3 mA
BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.
Base current
IB = (3.3 − 0.7)/100 kΩ = 26 µA
Saturated or active?
β·IB is smaller than IC(sat), so the transistor stays active.
β·IB = 1.3 mA
IC(sat) = (12 − 0.2)/470 = 25.11 mA
Collector current
IC = β·IB = 1.3 mA
Answer
IC = 1.3 mA
The transistor is active, so the load is not fully switched on.
3.Op-amp circuits
Answer: Vout = −4.5 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Inverting input follows the input
V₋ = V₊ = −1.5 V
I = V₋/R1 = −1.5/1 = −1.5 mA
Output voltage
The current through R₁ also flows through Rf.
Vout = V₋ + I·Rf = −1.5 + (−1.5)·2 = −4.5 V
Answer
Vout = −4.5 V
4.Op-amp circuits
Answer: Vout = 0.8 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Voltage at the + input
V₊ = V2·R4/(R3 + R4) = 0.9·2/(1 + 2) = 0.6 V
Superpose the two inputs
With V₂ = 0, V₁ sees an inverting amplifier. With V₁ = 0, V₊ is amplified by the non-inverting gain 1 + R₂/R₁.
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
τ = L/R = 10 mH / 22 Ω = 0.4545 ms
i(∞) = Vs/R = 15/22 = 0.6818 A
Inductor voltage
At t = 0 the whole supply voltage appears across the inductor; it then decays to zero.
vL(t) = Vs·e−t/τ = 15·e−1/0.4545 = 1.662 V
Answer
vL = 1.662 V
6.RC & RL transients
Answer: vC = 4.767 V
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial value, final value, time constant
The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.
vC(0) = 2 V, vC(∞) = Vs = 6 V
τ = R·C = 1 kΩ · 68 µF = 68 ms
vC(t) = 6 + (2 − 6)·e−t/τ
Voltage at the given time
vC(80) = 6 + (−4)·e−80/68 = 4.767 V
Answer
vC = 4.767 V
7.Series & parallel resistors
Answer: IR2 = 1.058 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 20 + 20 = 40 Ω
R2 ∥ 40 = 6·40/(6+40) = 5.217 Ω
Req = R1 + 5.217 = 3 + 5.217 = 8.217 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 10/8.217 = 1.217 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 10 − 1.217·3 = 6.349 V
IR2 = VA/R2 = 6.349/6 = 1.058 A
Answer
IR2 = 1.058 A
8.Series & parallel resistors
Answer: IR1 = 0.8228 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 2 + 2 = 4 Ω
R4 ∥ 4 = 2.667 Ω
R3 + 2.667 = 22.67 Ω
R2 ∥ 22.67 = 6.939 Ω
Req = R1 + 6.939 = 4 + 6.939 = 10.94 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 9/10.94 = 0.8228 A
Answer
IR1 = 0.8228 A
9.DC-DC converters
Answer: ΔIL = 1.145 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 1 − 36/120 = 0.7
Inductor voltage during the on-time
While S is on, the inductor sits directly across Vin.
VL = 36 V
Ripple current
ΔIL = VL·D/(L·f) = 36·0.7/(220·10⁻⁶·100·10³) = 1.145 A
Answer
ΔIL = 1.145 A
10.DC-DC converters
Answer: C = 1.536 µF
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 19.2/48 = 0.4
Inductor ripple current
ΔIL = (48 − 19.2)·0.4/(150·10⁻⁶·250·10³) = 0.3072 A
Capacitance
C = 0.3072/(8·250·10³·100·10⁻³) = 1.536 µF
Answer
C = 1.536 µF
11.Wheatstone bridge & strain gauges
Answer: Ig = −5742 µA
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Thévenin voltage
Vth = 12·(250/400 − 150/210) = −1.071 V
Thévenin resistance
Rth = R₁∥R₂ + R₃∥R₄ = 136.6 Ω
Galvanometer current
Ig = −1.071/(136.6 + 50) = −5742 µA
Answer
Ig = −5742 µA
12.Wheatstone bridge & strain gauges
Answer: ε = 200 µε
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Relative resistance change
ΔR/R = 0.42/1000 = 0.00042
Strain
ε = 0.00042/2.1 = 0.0002 = 200 µε
Answer
ε = 200 µε
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 4
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Group the 0s
Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.
(C′ + D′)
(B′ + D)
(A′ + B′)
(A + B + C)
Minimal POS form
F = (C′ + D′)(B′ + D)(A′ + B′)(A + B + C)
N = 4
Answer
N = 4
14.Digital logic: gates, K-maps & flip-flops
Answer: N = 4
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
Q after every edge
A JK flip-flop: 00 holds, 01 resets (Q = 0), 10 sets (Q = 1), 11 toggles.