Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
A 9.1 V Zener regulator is fed from 24 V through 220 Ω and supplies a 1000 Ω load. Find the Zener current IZ.
Vin = 24 VVZ = 9.1 VR = 220 ΩRL = 1000 Ω
IZ = mA
2.Diodes & transistorsHard
A 3.3 V Zener regulator must supply up to 50 mA to a load. The input can drop to 15 V, and the Zener needs at least 1 mA to regulate. Find the largest series resistance Rmax that keeps it regulating.
The op-amp is ideal and runs from ±15 V supplies; its output saturates at ±12 V. The non-inverting amplifier is driven by a sine wave. Find the largest input amplitude Vin,max (peak value) for which the output does not clip.
R1 = 22 kΩRf = 100 kΩVsat = ±12 V
Vin,max = V
4.Op-amp circuitsHard
The op-amp is ideal and runs from ±15 V supplies. The resistor ratios are not matched. Find the output voltage Vout.
The inductor carries no current before the switch closes at t = 0. Find the energy W stored in the inductor at t = 1 ms, in mJ.
Vs = 5 VR = 50 ΩL = 68 mHt = 1 ms
W = mJ
6.RC & RL transientsHard
The switch has been closed for a long time, so the circuit is in steady state. At t = 0 the switch opens. Find the current i2 through R2 at t = 200 ms.
An ideal buck converter turns 9 V into 3.6 V at a switching frequency of 40 kHz. Find the inductance L that keeps the peak-to-peak inductor ripple current at 0.3 A.
Vin = 9 VVo = 3.6 Vf = 40 kHzΔIL = 0.3 A
L = µH
10.DC-DC convertersHard
An ideal buck-boost converter turns 12 V into −4 V for a 20 Ω load at 500 kHz. The output capacitor is 47 µF. Find the peak-to-peak output voltage ripple ΔVo in mV.
Vin = 12 VVo = −4 Vf = 500 kHzC = 47 µFR = 20 Ω
ΔVo = mV
11.Wheatstone bridge & strain gaugesMedium
A bridge has four 470 Ω arms and Vs = 6 V. The sensor R₂ increases by ΔR = 0.94 Ω. Using the small-change approximation, find the output Vab in mV.
Vs = 6 VR = 470 ΩΔR = 0.94 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
A strain gauge (GF = 2) on a member with E = 210 GPa forms a quarter bridge excited with 2.5 V. The output reads 0.5 mV. Find the axial stress σ in MPa.
In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.
F = Σm(0, 3, 9, 10, 11, 14)
1AB = 00, CD = 00
2AB = 00, CD = 01
3AB = 00, CD = 11
4AB = 00, CD = 10
5AB = 01, CD = 00
6AB = 01, CD = 01
7AB = 01, CD = 11
8AB = 01, CD = 10
9AB = 11, CD = 00
10AB = 11, CD = 01
11AB = 11, CD = 11
12AB = 11, CD = 10
13AB = 10, CD = 00
14AB = 10, CD = 01
15AB = 10, CD = 11
16AB = 10, CD = 10
14.Digital logic: gates, K-maps & flip-flopsHard
A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.
Q₀ = 0JK
1clock edge 1
2clock edge 2
3clock edge 3
4clock edge 4
5clock edge 5
6clock edge 6
3Solutions
1.Diodes & transistors
Answer: IZ = 58.63 mA
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Resistor current
IR = 14.9/220 = 67.73 mA
Load current
IL = 9.1/1000 = 9.1 mA
Zener current
IZ = 67.73 − 9.1 = 58.63 mA
Answer
IZ = 58.63 mA
2.Diodes & transistors
Answer: Rmax = 229.4 Ω
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Worst-case current
IR = 50 + 1 = 51 mA
Largest resistance
Rmax = 11.7/0.051 = 229.4 Ω
Answer
Rmax = 229.4 Ω
3.Op-amp circuits
Answer: Vin,max = 2.164 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain
Av = 1 + Rf/R1 = 1 + 100/22 = 5.545
Largest input before clipping
Vin,max = Vsat/|Av| = 12/5.545 = 2.164 V
Answer
Vin,max = 2.164 V
4.Op-amp circuits
Answer: Vout = 11.14 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
τ = L/R = 68 mH / 50 Ω = 1.36 ms
i(∞) = Vs/R = 5/50 = 0.1 A
Current at the given time
i(t) = 0.1·(1 − e−1/1.36) = 0.05206 A
Stored energy
W = ½·L·i² = ½·68·0.05206² = 0.09216 mJ
Answer
W = 0.09216 mJ
6.RC & RL transients
Answer: i2 = 1.874 mA
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial capacitor voltage
In steady state the capacitor is an open circuit, so R₁ and R₂ form a voltage divider. The capacitor voltage cannot jump when the switch opens.
vC(0) = 20·1/(3.3 + 1) = 4.651 V
Time constant after the switch opens
τ = R2·C = 1·220 = 220 ms
Discharge
vC(t) = 4.651·e−200/220 = 1.874 V
i2 = vC/R2 = 1.874/1 = 1.874 mA
Answer
i2 = 1.874 mA
7.Series & parallel resistors
Answer: IR2 = 1.842 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 4 + 10 = 14 Ω
R2 ∥ 14 = 3·14/(3+14) = 2.471 Ω
Req = R1 + 2.471 = 2 + 2.471 = 4.471 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 10/4.471 = 2.237 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 10 − 2.237·2 = 5.526 V
IR2 = VA/R2 = 5.526/3 = 1.842 A
Answer
IR2 = 1.842 A
8.Series & parallel resistors
Answer: IR2 = 2.693 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 25 + 15 = 40 Ω
R4 ∥ 40 = 6.667 Ω
R3 + 6.667 = 12.67 Ω
R2 ∥ 12.67 = 4.071 Ω
Req = R1 + 4.071 = 5 + 4.071 = 9.071 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 36/9.071 = 3.969 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 36 − 3.969·5 = 16.16 V
IR2 = VA/R2 = 16.16/6 = 2.693 A
Answer
IR2 = 2.693 A
9.DC-DC converters
Answer: L = 180 µH
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 3.6/9 = 0.4
Inductance
L = 5.4·0.4/(0.3·40·10³) = 180 µH
Answer
L = 180 µH
10.DC-DC converters
Answer: ΔVo = 2.128 mV
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 4/(12 + 4) = 0.25
Load current
Io = 4/20 = 0.2 A
Output ripple
ΔVo = 0.2·0.25/(500·10³·47·10⁻⁶) = 2.128 mV
Answer
ΔVo = 2.128 mV
11.Wheatstone bridge & strain gauges
Answer: Vab = 3 mV
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Relative change
ΔR/R = 0.94/470 = 0.002
Linearised output
Vab ≈ 6·0.002/4 = 3 mV
Answer
Vab = 3 mV
The exact value is 2.997 mV; the approximation is good while ΔR/R is small.
12.Wheatstone bridge & strain gauges
Answer: σ = 84 MPa
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Strain
ε = 4·0.0005/(2.5·2) = 0.0004
Stress
σ = 210·10³ MPa·0.0004 = 84 MPa
Answer
σ = 84 MPa
13.Digital logic: gates, K-maps & flip-flops
Answer: AB = 00, CD = 00
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Neighbours of each 1
A 1 with a neighbouring 1 can join a group of two or more.
m0: m1, m2, m4, m8 → 0
The isolated 1
m0 = A′B′C′D′ → AB = 00, CD = 00
Answer
AB = 00, CD = 00
14.Digital logic: gates, K-maps & flip-flops
Answer: clock edge 3
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
Q after every edge
A JK flip-flop: 00 holds, 01 resets (Q = 0), 10 sets (Q = 1), 11 toggles.