Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

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1Formulas and methods

Diodes & transistors

Diode (constant drop)
VD = 0.7 V when conducting
Active region
VBE = 0.7 V, IC = β·IB, IE = (β + 1)·IB
Fixed bias
IB = (VCC − 0.7)/RB
Divider bias
IB = (VTH − 0.7)/(RTH + (β + 1)RE)
Thévenin of the divider
VTH = VCC·R2/(R1 + R2), RTH = R1∥R2
Collector loop
VCE = VCC − ICRC − IERE
Saturation
IC(sat) = (VCC − VCE(sat))/RC, IB ≥ IC(sat)/β

Op-amp circuits

Inverting amplifier
Vout = −(Rf/Rin)·Vin
Non-inverting amplifier
Vout = (1 + Rf/R1)·Vin
Summing amplifier
Vout = −Rf(V1/R1 + V2/R2)
Ideal op-amp
V+ = V−, Iin = 0

RC & RL transients

Time constant
τ = RC | τ = L/R
Response
x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ
Capacitor at DC
open circuit; vC cannot jump
Inductor at DC
short circuit; iL cannot jump
Settled
t ≈ 5τ

Method

  1. Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
  2. Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
  3. Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
  4. Use x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ.

Series & parallel resistors

Resistors in series
Req = R1 + R2 + …
Resistors in parallel
1/Req = 1/R1 + 1/R2 + …
Two in parallel
Req = R1R2 / (R1 + R2)
Ohm's law
V = I·R
Power
P = V·I = I²R = V²/R

Method

  1. Start at the end of the network furthest from the terminals.
  2. Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
  3. Redraw the circuit after each step.
  4. Repeat until one resistor is left between the terminals.

DC-DC converters

Buck
Vo = D·Vin
Boost
Vo = Vin/(1 − D)
Inverting buck-boost
|Vo| = Vin·D/(1 − D)
Ideal power balance
VinIin = VoIo
Inductor ripple
ΔIL = VL,on·D/(L·f); buck Vin − Vo, boost and buck-boost Vin
Average inductor current
buck Io; boost and buck-boost Io/(1 − D)
Output ripple
buck ΔIL/(8fC); boost and buck-boost Io·D/(fC)
CCM boundary
buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

  1. Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
  2. Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
  3. Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
  4. For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.

Wheatstone bridge & strain gauges

Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε

Method

  1. Treat the bridge as two voltage dividers across the same supply.
  2. For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
  3. For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
  4. For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium
RC​ = 2.7 kΩβ = 150RE​ = 2.2 kΩVCC​ = 18 VR1​ = 33 kΩR2​ = 15 kΩ

An NPN transistor with β = 150 has voltage-divider bias from VCC = 18 V: R₁ = 33 kΩ from VCC to the base and R₂ = 15 kΩ from the base to ground. The collector resistor is RC = 2.7 kΩ and the emitter resistor is RE = 2.2 kΩ. Take VBE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector–emitter voltage VCE.

VCC = 18 VR1 = 33 kΩR2 = 15 kΩRC = 2.7 kΩRE = 2.2 kΩβ = 150
VCE = V
2.Diodes & transistorsHard
V (V)I (mA)0.7627.27Q = ?

A diode is modelled as 0.7 V in series with 25 Ω (it conducts above 0.7 V). It is in series with a 220 Ω resistor across a 6 V supply. Find the operating current ID where the diode line meets the load line.

Vs = 6 VR = 220 ΩV0 = 0.7 Vrd = 25 Ω
ID = mA
3.Op-amp circuitsMedium
−+Vout​R2​ = 1 kΩV1​ = −0.1 VR1​ = 4.7 kΩV2​ = −1.1 VR3​ = 4.7 kΩR4​ = 1 kΩ

The difference amplifier uses an ideal op-amp with ±15 V supplies, with R3 = R1 and R4 = R2. Find the voltage V− at the inverting input.

V1 = −0.1 VV2 = −1.1 VR1 = R3 = 4.7 kΩR2 = R4 = 1 kΩ
V− = V
4.Op-amp circuitsHard
−+Vout​R2​ = 4.7 kΩV1​ = 1.9 VR1​ = 1 kΩV2​ = 0.9 VR3​ = 100 kΩR4​ = 10 kΩ

The op-amp is ideal and runs from ±15 V supplies. The resistor ratios are not matched. Find the output voltage Vout.

V1 = 1.9 VV2 = 0.9 VR1 = 1 kΩR2 = 4.7 kΩR3 = 100 kΩR4 = 10 kΩ
Vout = V
5.RC & RL transientsMedium
+−Vs​6 Vt = 0R1​ = 3.3 kΩR2​ = 1 kΩC10 µF+−vC​

The source Vₛ charges the capacitor through R₁, and R₂ is connected in parallel with C. The capacitor is uncharged when the switch closes at t = 0. Find the capacitor voltage vC at t = 5 ms.

Vs = 6 VR1 = 3.3 kΩR2 = 1 kΩC = 10 µFt = 5 ms
vC = V
6.RC & RL transientsHard
+−Vs​9 Vopens at t = 0R1​ = 4.7 kΩR2​ = 4.7 kΩi2​C68 µF+−vC​

The switch has been closed for a long time, so the circuit is in steady state. At t = 0 the switch opens. Find the current i2 through R2 at t = 750 ms.

Vs = 9 VR1 = 4.7 kΩR2 = 4.7 kΩC = 68 µFt = 750 ms
i2 = mA
7.Series & parallel resistorsMedium
R1​ = 4 ΩR3​ = 2 Ω+−V1​6 VR2​8 ΩIR2​AR4​10 ΩB

Find the current IR2 through R2.

V1 = 6 VR1 = 4 ΩR2 = 8 ΩR3 = 2 ΩR4 = 10 Ω
IR2 = A
8.Series & parallel resistorsHard
R1​ = 3 ΩIR1​R3​ = 8 ΩR5​ = 3 Ω+−V1​12 VR2​10 ΩAR4​2 ΩBR6​2 Ω

Find the current IR1 delivered by the source, which flows through R1.

V1 = 12 VR1 = 3 ΩR2 = 10 ΩR3 = 8 ΩR4 = 2 ΩR5 = 3 ΩR6 = 2 Ω
IR1 = A
9.DC-DC convertersMedium
tiL​Imax​Imin​ΔI = ?DTT2T

An ideal boost converter turns 15 V into 20 V at 250 kHz with L = 220 µH. Find the peak-to-peak inductor ripple current ΔIL.

Vin​ = 15 VVo​ = 20 Vf = 250 kHzL = 220 µH
ΔIL = A
10.DC-DC convertersHard
+−12 VSLC = 47 µFR = 4 Ω−+−18 V

An ideal buck-boost converter turns 12 V into −18 V for a 4 Ω load at 25 kHz. The output capacitor is 47 µF. Find the peak-to-peak output voltage ripple ΔVo in mV.

Vin​ = 12 VVo​ = −18 Vf = 25 kHzC = 47 µFR = 4 Ω
ΔVo = mV
11.Wheatstone bridge & strain gaugesMedium
+−9 V470 Ω470 Ω + ΔR470 Ω470 Ωab+−Vab​ = ?

A bridge has four 470 Ω arms and Vs = 9 V. The sensor R₂ increases by ΔR = 70.5 Ω. Find the exact output Vab in mV.

Vs = 9 VR = 470 ΩΔR = 70.5 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
+−3 V120 Ω − ΔR120 Ω + ΔR120 Ω120 Ωab+−Vo​ = ?

A bridge with 120 Ω arms is excited with 3 V and has two active gauges in adjacent arms, one in tension and one in compression (half bridge). The gauge factor is 2.1 and the strain is 750 µε. Find the bridge output Vo in mV.

Vs = 3 VGF = 2.1ε = 750 µε
Vo = mV
13.Digital logic: gates, K-maps & flip-flopsMedium
ABC000111100101324576

Simplify F = A′C + A′B′C + B′C′ to its minimal sum-of-products form. How many literals L does the simplified expression contain?

F = A′C + A′B′C + B′C′
L =
14.Digital logic: gates, K-maps & flip-flopsHard
FFQ0​Q0​FFQ1​Q1​FFQ2​Q2​FFQ3​Q3​FFQ4​Q4​CLKMOD-25

A mod-25 counter is built from the minimum number of flip-flops. How many of the possible states U are never used?

N = 25
U =

3Solutions

1.Diodes & transistors

Answer: VCE = 7.4 V

BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.

Thévenin equivalent of the divider

VTH = 18·15/(33 + 15) = 5.625 V
RTH = 33·15/(33 + 15) = 10.31 kΩ

Base current

KVL around the base loop; the emitter current is (β + 1)·IB.

IB = (5.625 − 0.7)/(10.31 + 151·2.2) = 14.38 µA

Collector current

IC = 150·14.38 µA = 2.157 mA
IE = 151·14.38 µA = 2.171 mA

Collector–emitter voltage

VCE = 18 − 2.157·2.7 − 2.171·2.2 = 7.4 V

Answer

VCE = 7.4 V
2.Diodes & transistors

Answer: ID = 21.63 mA

LED and diode circuits: a forward-biased LED drops roughly its forward voltage VF (about 2 V for red, 3 V for blue or white), whatever the current. A series resistor sets the current: R = (Vs − n·VF)/I for n LEDs in series. With a more exact diode model V = V₀ + I·rd, the operating point is where the diode line meets the load line I = (Vs − V)/R, so I = (Vs − V₀)/(R + rd).

Combine the two equations

6 = 0.7 + I·(220 + 25)

Operating current

ID = 5.3/245 = 21.63 mA
VD = 0.7 + 0.02163·25 = 1.241 V

Answer

ID = 21.63 mA
3.Op-amp circuits

Answer: V− = −0.193 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Voltage at the inputs

R₃ and R₄ carry the same current, so they form a voltage divider; feedback makes V₋ = V₊.

V₊ = V2·R4/(R3 + R4) = −1.1·1/(4.7 + 1) = −0.193 V
V₋ = V₊

Answer

V− = −0.193 V
4.Op-amp circuits

Answer: Vout = −8.464 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Voltage at the + input

V₊ = V2·R4/(R3 + R4) = 0.9·10/(100 + 10) = 0.08182 V

Superpose the two inputs

With V₂ = 0, V₁ sees an inverting amplifier. With V₁ = 0, V₊ is amplified by the non-inverting gain 1 + R₂/R₁.

Vout = −(4.7/1)·1.9 + (1 + 4.7/1)·0.08182 = −8.93 + 0.4664 = −8.464 V

Answer

Vout = −8.464 V
5.RC & RL transients

Answer: vC = 0.668 V

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Thévenin equivalent seen by the capacitor

Short the source to find Rth; open the capacitor to find the voltage it will settle at.

Rth = R1 ∥ R2 = 3.3·1/(3.3 + 1) = 0.7674 kΩ
vC(∞) = 6·1/(3.3 + 1) = 1.395 V

Time constant

τ = Rth·C = 0.7674·10 = 7.674 ms

Charging curve

vC(t) = 1.395·(1 − e−5/7.674) = 0.668 V

Answer

vC = 0.668 V
6.RC & RL transients

Answer: i2 = 0.09161 mA

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Initial capacitor voltage

In steady state the capacitor is an open circuit, so R₁ and R₂ form a voltage divider. The capacitor voltage cannot jump when the switch opens.

vC(0) = 9·4.7/(4.7 + 4.7) = 4.5 V

Time constant after the switch opens

τ = R2·C = 4.7·68 = 319.6 ms

Discharge

vC(t) = 4.5·e−750/319.6 = 0.4306 V
i2 = vC/R2 = 0.4306/4.7 = 0.09161 mA

Answer

i2 = 0.09161 mA
7.Series & parallel resistors

Answer: IR2 = 0.4091 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 4 ΩR3​ = 2 Ω+−V1​6 VR2​8 ΩAR4​10 ΩB

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R3 + R4 = 2 + 10 = 12 Ω
R2 ∥ 12 = 8·12/(8+12) = 4.8 Ω
Req = R1 + 4.8 = 4 + 4.8 = 8.8 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 6/8.8 = 0.6818 A

Current through R₂

Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.

VA = V1 − IR1·R1 = 6 − 0.6818·4 = 3.273 V
IR2 = VA/R2 = 3.273/8 = 0.4091 A

Answer

IR2 = 0.4091 A
8.Series & parallel resistors

Answer: IR1 = 1.528 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 3 ΩR3​ = 8 ΩR5​ = 3 Ω+−V1​12 VR2​10 ΩAR4​2 ΩBR6​2 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R5 + R6 = 3 + 2 = 5 Ω
R4 ∥ 5 = 1.429 Ω
R3 + 1.429 = 9.429 Ω
R2 ∥ 9.429 = 4.853 Ω
Req = R1 + 4.853 = 3 + 4.853 = 7.853 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 12/7.853 = 1.528 A

Answer

IR1 = 1.528 A
9.DC-DC converters

Answer: ΔIL = 0.06818 A

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 1 − 15/20 = 0.25

Inductor voltage during the on-time

While S is on, the inductor sits directly across Vin.

VL = 15 V

Ripple current

ΔIL = VL·D/(L·f) = 15·0.25/(220·10⁻⁶·250·10³) = 0.06818 A

Answer

ΔIL = 0.06818 A
10.DC-DC converters

Answer: ΔVo = 2298 mV

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 18/(12 + 18) = 0.6

Load current

Io = 18/4 = 4.5 A

Output ripple

ΔVo = 4.5·0.6/(25·10³·47·10⁻⁶) = 2298 mV

Answer

ΔVo = 2298 mV
11.Wheatstone bridge & strain gauges

Answer: Vab = 314 mV

Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.

Node voltages

Va = 9·540.5/1011 = 4.814 V
Vb = 4.5 V

Output

Vab = 314 mV

Answer

Vab = 314 mV

The linear estimate Vs·ΔR/(4R) = 337.5 mV is 7.5 % too high: a quarter bridge is not quite linear.

12.Wheatstone bridge & strain gauges

Answer: Vo = 2.363 mV

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Relative resistance change

ΔR/R = 2.1·750·10⁻⁶ = 0.001575

Bridge output

Vo = Vs·GF·ε/2 = 3·0.001575/2 = 2.363 mV

Answer

Vo = 2.363 mV
13.Digital logic: gates, K-maps & flip-flops

Answer: L = 4

Boolean algebra: the rules that simplify expressions are X + X′ = 1 and X·X′ = 0, X + X = X, absorption X + X·Y = X, the combining rule X·Y + X·Y′ = X, X + X′Y = X + Y and the consensus theorem XY + X′Z + YZ = XY + X′Z. De Morgan's laws turn (X·Y)′ into X′ + Y′ and (X + Y)′ into X′·Y′. A Karnaugh map applies these rules graphically: every group of two neighbouring cells is one use of XY + XY′ = X.

Minterms of the expression

A′C → m(1, 3)
A′B′C → m(1)
B′C′ → m(0, 4)
ABC00011110011011130214050706

Group and read off

F = B′C′ + A′C

Count the literals

L = 4

Answer

L = 4
14.Digital logic: gates, K-maps & flip-flops

Answer: U = 7

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Number of flip-flops

2ⁿ ≥ 25 → n = 5 (2⁵ = 32)

Unused states

U = 32 − 25 = 7

Answer

U = 7

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