Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 100 is biased by a base resistor RB = 330 kΩ from the supply VCC = 15 V. The collector resistor is RC = 1.2 kΩ and the emitter is grounded. Take VBE = 0.7 V and assume the transistor is in the active region. Find the collector–emitter voltage VCE.
A 6.2 V Zener regulator has a 470 Ω series resistor. The input can rise to 21 V, and the load may be disconnected. Find the largest power PZ,max the Zener must dissipate.
Vin,max = 21 VVZ = 6.2 VR = 470 Ω
PZ,max = mW
3.Op-amp circuitsMedium
The op-amp is ideal and runs from ±15 V supplies; its output saturates at ±14 V. The non-inverting amplifier is driven by a sine wave. Find the largest input amplitude Vin,max (peak value) for which the output does not clip.
R1 = 1 kΩRf = 22 kΩVsat = ±14 V
Vin,max = V
4.Op-amp circuitsHard
The summing amplifier uses an ideal op-amp with ±15 V supplies. Find the output voltage Vout.
The inductor carries no current before the switch closes at t = 0. How long after the switch closes does the current reach 50% of its final value? Find t.
Vs = 9 VR = 20 ΩL = 150 mH
t = ms
6.RC & RL transientsHard
The switch across R2 has been open for a long time, so the inductor current is steady. At t = 0 the switch closes and shorts out R2. How long after t = 0 does the inductor current reach 0.211 A? Find t.
Vs = 9 VR1 = 33 ΩR2 = 20 ΩL = 100 mH
t = ms
7.Series & parallel resistorsMedium
Find the current IR1 delivered by the source, which flows through R1.
V1 = 24 VR1 = 2 ΩR2 = 4 ΩR3 = 12 ΩR4 = 4 Ω
IR1 = A
8.Series & parallel resistorsHard
Find the current IR1 delivered by the source, which flows through R1.
An ideal buck converter turns 24 V into 9.6 V at a switching frequency of 200 kHz. Find the inductance L that keeps the peak-to-peak inductor ripple current at 0.4 A.
Vin = 24 VVo = 9.6 Vf = 200 kHzΔIL = 0.4 A
L = µH
10.DC-DC convertersHard
An ideal buck converter turns 15 V into 7.5 V for a 10 Ω load at 500 kHz. Find the smallest inductance Lcrit for continuous conduction.
Vin = 15 VVo = 7.5 Vf = 500 kHzR = 10 Ω
Lcrit = µH
11.Wheatstone bridge & strain gaugesMedium
A bridge has four 1000 Ω arms and Vs = 5 V. The sensor R₂ increases by ΔR = 100 Ω. Find the exact output Vab in mV.
Vs = 5 VR = 1000 ΩΔR = 100 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
A quarter bridge (one active gauge, GF = 2.12) is excited with 10 V. The largest strain to be measured is 500 µε, and it must give 2.5 V at the input of an analogue-to-digital converter. Find the amplifier gain G.
A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = C′, I₁ = 0, I₂ = 1, I₃ = C. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.
I₀ = C′I₁ = 0I₂ = 1I₃ = C
N =
14.Digital logic: gates, K-maps & flip-flopsHard
A 100 kHz clock drives a mod-5 counter. Find the frequency fout of its most significant output, which completes one cycle per counting cycle.
fclk = 100 kHzN = 5
fout = kHz
3Solutions
1.Diodes & transistors
Answer: VCE = 9.8 V
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Worst-case Zener current
IZ = 14.8/470 = 31.49 mA
Zener power
PZ = 6.2·31.49 = 195.2 mW
Answer
PZ,max = 195.2 mW
3.Op-amp circuits
Answer: Vin,max = 0.6087 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain
Av = 1 + Rf/R1 = 1 + 22/1 = 23
Largest input before clipping
Vin,max = Vsat/|Av| = 14/23 = 0.6087 V
Answer
Vin,max = 0.6087 V
4.Op-amp circuits
Answer: Vout = −7.943 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Input currents
V₋ = 0, so each input resistor has its full input voltage across it.
I1 = V1/R1 = 1.9/100 = 0.019 mA
I2 = V2/R2 = 0.3/2 = 0.15 mA
If = I1 + I2 = 0.169 mA
Output voltage
Vout = −Rf·If = −47·0.169 = −7.943 V
Answer
Vout = −7.943 V
5.RC & RL transients
Answer: t = 5.199 ms
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
τ = L/R = 150 mH / 20 Ω = 7.5 ms
i(∞) = Vs/R = 9/20 = 0.45 A
Solve for the time
0.5 = 1 − e−t/τ → t = −τ·ln(1 − 0.5)
t = −7.5·ln(0.5) = 5.199 ms
Answer
t = 5.199 ms
6.RC & RL transients
Answer: t = 1.549 ms
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial value, final value, time constant
Before t = 0 both resistors are in the loop; afterwards the closed switch bypasses R₂.
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 12 + 4 = 16 Ω
R2 ∥ 16 = 4·16/(4+16) = 3.2 Ω
Req = R1 + 3.2 = 2 + 3.2 = 5.2 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 24/5.2 = 4.615 A
Answer
IR1 = 4.615 A
8.Series & parallel resistors
Answer: IR1 = 0.1544 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 15 + 25 = 40 Ω
R4 ∥ 40 = 1.905 Ω
R3 + 1.905 = 5.905 Ω
R2 ∥ 5.905 = 2.385 Ω
Req = R1 + 2.385 = 30 + 2.385 = 32.38 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 5/32.38 = 0.1544 A
Answer
IR1 = 0.1544 A
9.DC-DC converters
Answer: L = 72 µH
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 9.6/24 = 0.4
Inductance
L = 14.4·0.4/(0.4·200·10³) = 72 µH
Answer
L = 72 µH
10.DC-DC converters
Answer: Lcrit = 5 µH
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 7.5/15 = 0.5
Boundary condition
Set the average inductor current equal to half the ripple current and solve for L.
Lcrit = (1 − D)·R/(2f)
Critical inductance
Lcrit = (1 − 0.5)·10/(2500·10³) = 5 µH
Answer
Lcrit = 5 µH
11.Wheatstone bridge & strain gauges
Answer: Vab = 119 mV
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Node voltages
Va = 5·1100/2100 = 2.619 V
Vb = 2.5 V
Output
Vab = 119 mV
Answer
Vab = 119 mV
The linear estimate Vs·ΔR/(4R) = 125 mV is 5 % too high: a quarter bridge is not quite linear.
12.Wheatstone bridge & strain gauges
Answer: G = 943.4
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Bridge output at full scale
Vo = 2.65 mV
Gain
G = 2.5/0.00265 = 943.4
Answer
G = 943.4
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 4
Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.
Output expression
F = A′B′C′ + AB′ + ABC
Rows with F = 1
ABC = 000, 100, 101, 111
N = 4
Answer
N = 4
14.Digital logic: gates, K-maps & flip-flops
Answer: fout = 20 kHz
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.