Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

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1Formulas and methods

Diodes & transistors

Diode (constant drop)
VD = 0.7 V when conducting
Active region
VBE = 0.7 V, IC = β·IB, IE = (β + 1)·IB
Fixed bias
IB = (VCC − 0.7)/RB
Divider bias
IB = (VTH − 0.7)/(RTH + (β + 1)RE)
Thévenin of the divider
VTH = VCC·R2/(R1 + R2), RTH = R1∥R2
Collector loop
VCE = VCC − ICRC − IERE
Saturation
IC(sat) = (VCC − VCE(sat))/RC, IB ≥ IC(sat)/β

Op-amp circuits

Inverting amplifier
Vout = −(Rf/Rin)·Vin
Non-inverting amplifier
Vout = (1 + Rf/R1)·Vin
Summing amplifier
Vout = −Rf(V1/R1 + V2/R2)
Ideal op-amp
V+ = V−, Iin = 0

RC & RL transients

Time constant
τ = RC | τ = L/R
Response
x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ
Capacitor at DC
open circuit; vC cannot jump
Inductor at DC
short circuit; iL cannot jump
Settled
t ≈ 5τ

Method

  1. Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
  2. Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
  3. Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
  4. Use x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ.

Series & parallel resistors

Resistors in series
Req = R1 + R2 + …
Resistors in parallel
1/Req = 1/R1 + 1/R2 + …
Two in parallel
Req = R1R2 / (R1 + R2)
Ohm's law
V = I·R
Power
P = V·I = I²R = V²/R

Method

  1. Start at the end of the network furthest from the terminals.
  2. Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
  3. Redraw the circuit after each step.
  4. Repeat until one resistor is left between the terminals.

DC-DC converters

Buck
Vo = D·Vin
Boost
Vo = Vin/(1 − D)
Inverting buck-boost
|Vo| = Vin·D/(1 − D)
Ideal power balance
VinIin = VoIo
Inductor ripple
ΔIL = VL,on·D/(L·f); buck Vin − Vo, boost and buck-boost Vin
Average inductor current
buck Io; boost and buck-boost Io/(1 − D)
Output ripple
buck ΔIL/(8fC); boost and buck-boost Io·D/(fC)
CCM boundary
buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

  1. Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
  2. Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
  3. Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
  4. For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.

Wheatstone bridge & strain gauges

Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε

Method

  1. Treat the bridge as two voltage dividers across the same supply.
  2. For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
  3. For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
  4. For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium
+−12 V330 Ω9.1 V3300 ΩIZ​ = ?

A 9.1 V Zener regulator is fed from 12 V through 330 Ω and supplies a 3300 Ω load. Find the Zener current IZ.

Vin = 12 VVZ = 9.1 VR = 330 ΩRL = 3300 Ω
IZ = mA
2.Diodes & transistorsHard
RC​ = 100 Ωβ = 150IC​ = ?VCC​ = 12 V5 VRB​ = 220 kΩ

An NPN transistor with β = 150 switches a 100 Ω load resistor connected between VCC = 12 V and its collector. The emitter is grounded. The base is driven from a 5 V logic output through a base resistor RB = 220 kΩ. Take VBE = 0.7 V and VCE(sat) = 0.2 V. Find the collector current IC in mA when the input is high. Decide first whether the transistor is saturated.

VCC = 12 VRC = 100 Ωβ = 150Vin = 5 VVBE = 0.7 VVCE(sat) = 0.2 VRB = 220 kΩ
IC = mA
3.Op-amp circuitsMedium
−+Vout​R2​ = 10 kΩV1​ = 0.8 VR1​ = 2 kΩV2​ = 3 VR3​ = 2 kΩR4​ = 10 kΩ

The difference amplifier uses an ideal op-amp with ±15 V supplies, with R3 = R1 and R4 = R2. Find the voltage V− at the inverting input.

V1 = 0.8 VV2 = 3 VR1 = R3 = 2 kΩR2 = R4 = 10 kΩ
V− = V
4.Op-amp circuitsHard
−+Vout​R2​ = 4.7 kΩV1​ = −1.6 VR1​ = 10 kΩV2​ = −1 VR3​ = 2 kΩR4​ = 47 kΩ

The op-amp is ideal and runs from ±15 V supplies. The resistor ratios are not matched. Find the output voltage Vout.

V1 = −1.6 VV2 = −1 VR1 = 10 kΩR2 = 4.7 kΩR3 = 2 kΩR4 = 47 kΩ
Vout = V
5.RC & RL transientsMedium
+−Vs​15 Vt = 0R = 15 ΩL33 mHi(t)

The inductor carries no current before the switch closes at t = 0. Find the energy W(∞) stored in the inductor once the circuit has settled, in mJ.

Vs = 15 VR = 15 ΩL = 33 mH
W(∞) = mJ
6.RC & RL transientsHard
+−Vs​9 Vt = 0R = 4.7 kΩC?+−vC​

A timer starts charging an uncharged capacitor through a resistor from a 9 V supply at t = 0. It must trigger when the capacitor voltage reaches 8.1 V, exactly 25 ms after the start. With R = 4.7 kΩ, find the capacitance C needed.

Vs = 9 VVth = 8.1 VT = 25 msR = 4.7 kΩ
C = µF
7.Series & parallel resistorsMedium
R1​ = 5 ΩR3​ = 4 Ω+−V1​15 VR2​10 ΩIR2​AR4​15 ΩB

Find the current IR2 through R2.

V1 = 15 VR1 = 5 ΩR2 = 10 ΩR3 = 4 ΩR4 = 15 Ω
IR2 = A
8.Series & parallel resistorsHard
R1​ = 10 ΩR3​ = 6 ΩR5​ = 4 Ω+−V1​36 VR2​4 ΩIR2​AR4​3 ΩBR6​25 Ω

Find the current IR2 through R2.

V1 = 36 VR1 = 10 ΩR2 = 4 ΩR3 = 6 ΩR4 = 3 ΩR5 = 4 ΩR6 = 25 Ω
IR2 = A
9.DC-DC convertersMedium
+−36 VLSCR = 2.5 Ω+−72 V

An ideal boost converter turns 36 V into 72 V for a 2.5 Ω load. Find the average inductor current IL.

Vin​ = 36 VVo​ = 72 VR = 2.5 Ω
IL = A
10.DC-DC convertersHard
tiL​Imax​Io​DTT2T

A buck converter turns 12 V into 3.6 V at 25 kHz with L = 10 µH. Find the smallest load current Io,min for which it stays in continuous conduction.

Vin​ = 12 VVo​ = 3.6 Vf = 25 kHzL = 10 µH
Io,min = A
11.Wheatstone bridge & strain gaugesMedium
+−6 V330 Ω330 Ω + ΔR330 Ω330 Ωab+−Vab​ = ?

A bridge has four 330 Ω arms and Vs = 6 V. The sensor R₂ increases by ΔR = 3.3 Ω. Using the small-change approximation, find the output Vab in mV.

Vs = 6 VR = 330 ΩΔR = 3.3 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
+−V350 Ω350 Ω + ΔR350 Ω350 Ωab+−

A 350 Ω strain gauge with gauge factor 2 is bonded to a steel bar. Under load its resistance rises by 1.05 Ω. Find the strain ε in microstrain (µε).

R = 350 ΩGF = 2ΔR = 1.05 Ω
ε = µε
13.Digital logic: gates, K-maps & flip-flopsMedium
MUXCI0​C′I1​0I2​CI3​ABS1​S0​F

A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = C, I₁ = C′, I₂ = 0, I₃ = C. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.

I₀ = CI₁ = C′I₂ = 0I₃ = C
N =
14.Digital logic: gates, K-maps & flip-flopsHard
CLKJK12345678

A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.

Q₀ = 0JK
  1. 1clock edge 1
  2. 2clock edge 2
  3. 3clock edge 3
  4. 4clock edge 4
  5. 5clock edge 5
  6. 6clock edge 6
  7. 7clock edge 7
  8. 8clock edge 8

3Solutions

1.Diodes & transistors

Answer: IZ = 6.03 mA

Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.

Resistor current

IR = 2.9/330 = 8.788 mA

Load current

IL = 9.1/3300 = 2.758 mA

Zener current

IZ = 8.788 − 2.758 = 6.03 mA

Answer

IZ = 6.03 mA
2.Diodes & transistors

Answer: IC = 2.932 mA

BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.

Base current

IB = (5 − 0.7)/220 kΩ = 19.55 µA

Saturated or active?

β·IB is smaller than IC(sat), so the transistor stays active.

β·IB = 2.932 mA
IC(sat) = (12 − 0.2)/100 = 118 mA

Collector current

IC = β·IB = 2.932 mA

Answer

IC = 2.932 mA

The transistor is active, so the load is not fully switched on.

3.Op-amp circuits

Answer: V− = 2.5 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Voltage at the inputs

R₃ and R₄ carry the same current, so they form a voltage divider; feedback makes V₋ = V₊.

V₊ = V2·R4/(R3 + R4) = 3·10/(2 + 10) = 2.5 V
V₋ = V₊

Answer

V− = 2.5 V
4.Op-amp circuits

Answer: Vout = −0.658 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Voltage at the + input

V₊ = V2·R4/(R3 + R4) = −1·47/(2 + 47) = −0.9592 V

Superpose the two inputs

With V₂ = 0, V₁ sees an inverting amplifier. With V₁ = 0, V₊ is amplified by the non-inverting gain 1 + R₂/R₁.

Vout = −(4.7/10)·(−1.6) + (1 + 4.7/10)·(−0.9592) = 0.752 + (−1.41) = −0.658 V

Answer

Vout = −0.658 V
5.RC & RL transients

Answer: W(∞) = 16.5 mJ

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Time constant and final current

Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.

τ = L/R = 33 mH / 15 Ω = 2.2 ms
i(∞) = Vs/R = 15/15 = 1 A

Stored energy

W(∞) = ½·L·i(∞)² = ½·33·1² = 16.5 mJ

Answer

W(∞) = 16.5 mJ
6.RC & RL transients

Answer: C = 2.31 µF

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Required time constant

8.1 = 9·(1 − e−25/τ) → τ = 25/ln(9/(9 − 8.1))
τ = 25/2.303 = 10.86 ms

Capacitance

kΩ times µF gives milliseconds.

C = τ/R = 10.86/4.7 = 2.31 µF

Answer

C = 2.31 µF
7.Series & parallel resistors

Answer: IR2 = 0.8507 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 5 ΩR3​ = 4 Ω+−V1​15 VR2​10 ΩAR4​15 ΩB

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R3 + R4 = 4 + 15 = 19 Ω
R2 ∥ 19 = 10·19/(10+19) = 6.552 Ω
Req = R1 + 6.552 = 5 + 6.552 = 11.55 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 15/11.55 = 1.299 A

Current through R₂

Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.

VA = V1 − IR1·R1 = 15 − 1.299·5 = 8.507 V
IR2 = VA/R2 = 8.507/10 = 0.8507 A

Answer

IR2 = 0.8507 A
8.Series & parallel resistors

Answer: IR2 = 1.937 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 10 ΩR3​ = 6 ΩR5​ = 4 Ω+−V1​36 VR2​4 ΩAR4​3 ΩBR6​25 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R5 + R6 = 4 + 25 = 29 Ω
R4 ∥ 29 = 2.719 Ω
R3 + 2.719 = 8.719 Ω
R2 ∥ 8.719 = 2.742 Ω
Req = R1 + 2.742 = 10 + 2.742 = 12.74 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 36/12.74 = 2.825 A

Current through R₂

Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.

VA = V1 − IR1·R1 = 36 − 2.825·10 = 7.747 V
IR2 = VA/R2 = 7.747/4 = 1.937 A

Answer

IR2 = 1.937 A
9.DC-DC converters

Answer: IL = 57.6 A

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 1 − 36/72 = 0.5

Load current

Io = 72/2.5 = 28.8 A

Inductor current

IL = Io/(1 − D) = 28.8/0.5 = 57.6 A

Answer

IL = 57.6 A
10.DC-DC converters

Answer: Io,min = 5.04 A

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 3.6/12 = 0.3

Ripple current

ΔIL = 3.6·0.7/(10·10⁻⁶·25·10³) = 10.08 A

Boundary load current

Io,min = ΔIL/2 = 5.04 A

Answer

Io,min = 5.04 A

Below this current the converter enters discontinuous conduction and Vo rises above D·Vin.

11.Wheatstone bridge & strain gauges

Answer: Vab = 15 mV

Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.

Relative change

ΔR/R = 3.3/330 = 0.01

Linearised output

Vab ≈ 6·0.01/4 = 15 mV

Answer

Vab = 15 mV

The exact value is 14.93 mV; the approximation is good while ΔR/R is small.

12.Wheatstone bridge & strain gauges

Answer: ε = 1500 µε

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Relative resistance change

ΔR/R = 1.05/350 = 0.003

Strain

ε = 0.003/2 = 0.0015 = 1500 µε

Answer

ε = 1500 µε
13.Digital logic: gates, K-maps & flip-flops

Answer: N = 3

Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.

Output expression

F = A′B′C + A′BC′ + ABC

Rows with F = 1

ABC = 001, 010, 111
N = 3

Answer

N = 3
14.Digital logic: gates, K-maps & flip-flops

Answer: clock edge 6

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Q after every edge

A JK flip-flop: 00 holds, 01 resets (Q = 0), 10 sets (Q = 1), 11 toggles.

1: J = 0, K = 1 → Q = 0
2: J = 0, K = 0 → Q = 0
3: J = 1, K = 1 → Q = 1
4: J = 0, K = 0 → Q = 1
5: J = 0, K = 0 → Q = 1
6: J = 0, K = 1 → Q = 0
7: J = 0, K = 0 → Q = 0
8: J = 0, K = 0 → Q = 0

First change from 1 to 0

clock edge 6

Answer

clock edge 6

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