Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.
A 12 V Zener regulator is fed from 20 V through 680 Ω and supplies a 2200 Ω load. Find the Zener current IZ.
A 5.1 V Zener regulator must supply up to 30 mA to a load. The input can drop to 9 V, and the Zener needs at least 2 mA to regulate. Find the largest series resistance Rmax that keeps it regulating.
The difference amplifier uses an ideal op-amp with ±15 V supplies, with R3 = R1 and R4 = R2. Find the voltage V− at the inverting input.
The summing amplifier uses an ideal op-amp with ±15 V supplies. Find the output voltage Vout.
The inductor carries no current before the switch closes at t = 0. How long after the switch closes does the current reach 50% of its final value? Find t.
Just before the switch closes at t = 0, the capacitor holds 8 V with the polarity shown. Find the capacitor voltage vC at t = 75 ms.
Find the equivalent resistance Req seen by the source V1.
Find the equivalent resistance Req seen by the source V1.
An ideal inverting buck-boost converter turns 36 V into −54 V at 100 kHz with L = 150 µH. Find the peak-to-peak inductor ripple current ΔIL.
An ideal boost converter turns 9 V into 30 V for a 25 Ω load at 250 kHz. The output capacitor is 10 µF. Find the peak-to-peak output voltage ripple ΔVo in mV.
A bridge with four 150 Ω arms is supplied with 5 V. When the sensor R₂ changes, the output reads Vab = 96.15 mV. Find the exact change ΔR of R₂.
A bridge with 350 Ω arms is excited with 5 V and has one active gauge (quarter bridge). The gauge factor is 2 and the strain is 250 µε. Find the bridge output Vo in mV.
Simplify F = ABC + A′BC + AB′C′ to its minimal sum-of-products form. How many literals L does the simplified expression contain?
A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown at 6 rising clock edges. How many times N does Q change state?
Answer: IZ = 6.31 mA
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Answer: Rmax = 121.9 Ω
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Answer: V− = 0.4545 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
R₃ and R₄ carry the same current, so they form a voltage divider; feedback makes V₋ = V₊.
Answer: Vout = −6.26 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
V₋ = 0, so each input resistor has its full input voltage across it.
Answer: t = 4.621 ms
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
Answer: vC = 7.133 V
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.
Answer: Req = 11.2 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
Answer: Req = 24.45 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
Answer: ΔIL = 1.44 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
While S is on, the inductor sits directly across Vin.
Answer: ΔVo = 336 mV
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Answer: ΔR = 12 Ω
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Answer: Vo = 0.625 mV
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Answer: L = 5
Boolean algebra: the rules that simplify expressions are X + X′ = 1 and X·X′ = 0, X + X = X, absorption X + X·Y = X, the combining rule X·Y + X·Y′ = X, X + X′Y = X + Y and the consensus theorem XY + X′Z + YZ = XY + X′Z. De Morgan's laws turn (X·Y)′ into X′ + Y′ and (X + Y)′ into X′·Y′. A Karnaugh map applies these rules graphically: every group of two neighbouring cells is one use of XY + XY′ = X.
Answer: N = 2
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
A JK flip-flop: 00 holds, 01 resets (Q = 0), 10 sets (Q = 1), 11 toggles.
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