Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

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1Formulas and methods

Diodes & transistors

Diode (constant drop): V_D = 0.7 V when conducting
Active region: V_BE = 0.7 V, I_C = β·I_B, I_E = (β + 1)·I_B
Fixed bias: I_B = (V_CC − 0.7)/R_B
Divider bias: I_B = (V_TH − 0.7)/(R_TH + (β + 1)R_E)
Thévenin of the divider: V_TH = V_CC·R₂/(R₁ + R₂), R_TH = R₁∥R₂
Collector loop: V_CE = V_CC − I_CR_C − I_ER_E
Saturation: I_C(sat) = (V_CC − V_CE(sat))/R_C, I_B ≥ I_C(sat)/β

Op-amp circuits

Inverting amplifier: V_out = −(R_f/R_in)·V_in
Non-inverting amplifier: V_out = (1 + R_f/R₁)·V_in
Summing amplifier: V_out = −R_f(V₁/R₁ + V₂/R₂)
Ideal op-amp: V₊ = V₋, I_in = 0

RC & RL transients

Time constant: τ = RC | τ = L/R
Response: x(t) = x(∞) + [x(0) − x(∞)]·e^−t/τ
Capacitor at DC: open circuit; v_C cannot jump
Inductor at DC: short circuit; i_L cannot jump
Settled: t ≈ 5τ

Method

Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
Use x(t) = x(∞) + [x(0) − x(∞)]·e^−t/τ.

Series & parallel resistors

Resistors in series: R_eq = R₁ + R₂ + …
Resistors in parallel: 1/R_eq = 1/R₁ + 1/R₂ + …
Two in parallel: R_eq = R₁R₂ / (R₁ + R₂)
Ohm's law: V = I·R
Power: P = V·I = I²R = V²/R

Method

Start at the end of the network furthest from the terminals.
Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
Redraw the circuit after each step.
Repeat until one resistor is left between the terminals.

DC-DC converters

Buck: V_o = D·V_in
Boost: V_o = V_in/(1 − D)
Inverting buck-boost: |V_o| = V_in·D/(1 − D)
Ideal power balance: V_inI_in = V_oI_o
Inductor ripple: ΔI_L = V_L,on·D/(L·f); buck V_in − V_o, boost and buck-boost V_in
Average inductor current: buck I_o; boost and buck-boost I_o/(1 − D)
Output ripple: buck ΔI_L/(8fC); boost and buck-boost I_o·D/(fC)
CCM boundary: buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔI_L = V_L·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔI_L/2.

Wheatstone bridge & strain gauges

Divider voltages: V_a = V_sR₂/(R₁ + R₂), V_b = V_sR₄/(R₃ + R₄)
Output: V_ab = V_a − V_b
Balance: R₁/R₂ = R₃/R₄
Slide-wire bridge: R/R_x = l/(100 − l)
Thévenin resistance: R_th = R₁∥R₂ + R₃∥R₄
Gauge factor: ΔR/R = GF·ε
Bridge output: quarter V_s·GF·ε/4, half V_s·GF·ε/2, full V_s·GF·ε
Small change, one arm: V_ab ≈ V_s·ΔR/(4R)
Stress: σ = E·ε

Method

Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find V_a and V_b from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use V_s·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates: A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules: X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan: (X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order: 00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells: loses k variables
4-to-1 multiplexer: F = A′B′I₀ + A′BI₁ + AB′I₂ + ABI₃
Flip-flops: D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters: n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; f_out = f_clk/N
Ripple counter: f_max = 1/(n·t_pd)
Ring and Johnson counters: n and 2n states

Method

For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium

An NPN transistor with β = 150 has voltage-divider bias from V_CC = 20 V: R₁ = 82 kΩ from V_CC to the base and R₂ = 15 kΩ from the base to ground. The collector resistor is R_C = 2.2 kΩ and the emitter resistor is R_E = 2.2 kΩ. Take V_BE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector–emitter voltage V_CE.

V_CC = 20 VR₁ = 82 kΩR₂ = 15 kΩR_C = 2.2 kΩR_E = 2.2 kΩβ = 150

V_CE = V

2.Diodes & transistorsHard

A 12 V Zener regulator must supply up to 30 mA to a load. The input can drop to 20 V, and the Zener needs at least 2 mA to regulate. Find the largest series resistance R_max that keeps it regulating.

V_in,min = 20 VV_Z = 12 VI_L,max = 30 mAI_Z,min = 2 mA

R_max = Ω

3.Op-amp circuitsMedium

The op-amp is ideal and runs from ±15 V supplies. Find the output voltage V_out.

V_in = 0.4 VR₁ = 4.7 kΩR_f = 47 kΩ

V_out = V

4.Op-amp circuitsHard

The summing amplifier uses an ideal op-amp with ±15 V supplies. Find the output voltage V_out.

V₁ = −1.2 VV₂ = −0.2 VR₁ = 1 kΩR₂ = 10 kΩR_f = 4.7 kΩ

V_out = V

5.RC & RL transientsMedium

The inductor carries no current before the switch closes at t = 0. Find the voltage v_L across the inductor at t = 1 ms.

V_s = 24 VR = 100 ΩL = 100 mHt = 1 ms

v_L = V

6.RC & RL transientsHard

Just before the switch closes at t = 0, the capacitor holds 6 V with the polarity shown. How long does it take for v_C to reach 7.6 V? Find t.

V_s = 10 VR = 1 kΩC = 100 µFv_C(0) = 6 V

t = ms

7.Series & parallel resistorsMedium

Find the current I_R1 delivered by the source, which flows through R₁.

V₁ = 6 VR₁ = 2 ΩR₂ = 5 ΩR₃ = 5 ΩR₄ = 2 Ω

I_R1 = A

8.Series & parallel resistorsHard

Find the equivalent resistance R_eq seen by the source V₁.

V₁ = 24 VR₁ = 20 ΩR₂ = 6 ΩR₃ = 25 ΩR₄ = 12 ΩR₅ = 5 ΩR₆ = 25 Ω

R_eq = Ω

9.DC-DC convertersMedium

An ideal buck converter turns 48 V into 36 V at a switching frequency of 40 kHz. Find the inductance L that keeps the peak-to-peak inductor ripple current at 0.2 A.

Vin = 48 VVo = 36 Vf = 40 kHzΔI_L = 0.2 A

L = µH

10.DC-DC convertersHard

A buck converter turns 24 V into 18 V at 250 kHz with L = 68 µH. Find the smallest load current I_o,min for which it stays in continuous conduction.

Vin = 24 VVo = 18 Vf = 250 kHzL = 68 µH

I_o,min = A

11.Wheatstone bridge & strain gaugesMedium

Find the Thévenin resistance R_th of the bridge shown, seen from the output terminals a and b.

V_s = 6 VR₁ = 1000 ΩR₂ = 60 ΩR₃ = 150 ΩR₄ = 250 Ω

R_th = Ω

12.Wheatstone bridge & strain gaugesHard

A quarter bridge (one active gauge, GF = 2) is excited with 3 V. The largest strain to be measured is 1500 µε, and it must give 3.3 V at the input of an analogue-to-digital converter. Find the amplifier gain G.

V_s = 3 VGF = 2ε_max = 1500 µεV_FS = 3.3 V

G =

13.Digital logic: gates, K-maps & flip-flopsMedium

Simplify F = A′B′C + A′BC + A′B′ + AC to its minimal sum-of-products form. How many literals L does the simplified expression contain?

F = A′B′C + A′BC + A′B′ + AC

L =

14.Digital logic: gates, K-maps & flip-flopsHard

Find the minimal SOP form of F(A, B, C, D) = Σm(0, 4, 7, 8, 10, 11, 12, 13, 14) + d(3, 9), where d marks the don't-care conditions. How many literals L does it contain?

F(A, B, C, D) = Σm(0, 4, 7, 8, 10, 11, 12, 13, 14) + d(3, 9)

L =

3Solutions

1.Diodes & transistors

Answer: V_CE = 15.41 V

BJT bias point: in the active region V_BE = 0.7 V, I_C = β·I_B and I_E = (β + 1)·I_B. Find I_B from the base loop with KVL, then I_C, then V_CE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent V_TH = V_CC·R₂/(R₁ + R₂), R_TH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.

Thévenin equivalent of the divider

V_TH = 20·15/(82 + 15) = 3.093 V

R_TH = 82·15/(82 + 15) = 12.68 kΩ

Base current

KVL around the base loop; the emitter current is (β + 1)·I_B.

I_B = (3.093 − 0.7)/(12.68 + 151·2.2) = 6.938 µA

Collector current

I_C = 150·6.938 µA = 1.041 mA

I_E = 151·6.938 µA = 1.048 mA

Collector–emitter voltage

V_CE = 20 − 1.041·2.2 − 1.048·2.2 = 15.41 V

Answer

V_CE = 15.41 V

2.Diodes & transistors

Answer: R_max = 250 Ω

Zener regulator: a reverse-biased Zener diode holds its voltage V_Z while its current stays above a minimum I_Z,min. The series resistor R takes the difference between input and output: I_R = (V_in − V_Z)/R. That current splits between the load, I_L = V_Z/R_L, and the Zener: I_Z = I_R − I_L. Design for the worst cases: the lowest input with the largest load must still leave I_Z,min, and the highest input with no load gives the largest Zener power P_Z = V_Z·I_Z.

Worst-case current

I_R = 30 + 2 = 32 mA

Largest resistance

R_max = 8/0.032 = 250 Ω

Answer

R_max = 250 Ω

3.Op-amp circuits

Answer: V_out = 4.4 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Inverting input follows the input

V₋ = V₊ = 0.4 V

I = V₋/R₁ = 0.4/4.7 = 0.08511 mA

Output voltage

The current through R₁ also flows through R_f.

V_out = V₋ + I·R_f = 0.4 + 0.08511·47 = 4.4 V

Answer

V_out = 4.4 V

4.Op-amp circuits

Answer: V_out = 5.734 V

Input currents

V₋ = 0, so each input resistor has its full input voltage across it.

I₁ = V₁/R₁ = −1.2/1 = −1.2 mA

I₂ = V₂/R₂ = −0.2/10 = −0.02 mA

I_f = I₁ + I₂ = −1.22 mA

Output voltage

V_out = −R_f·I_f = −4.7·(−1.22) = 5.734 V

Answer

V_out = 5.734 V

5.RC & RL transients

Answer: v_L = 8.829 V

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e^−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Time constant and final current

Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.

τ = L/R = 100 mH / 100 Ω = 1 ms

i(∞) = V_s/R = 24/100 = 0.24 A

Inductor voltage

At t = 0 the whole supply voltage appears across the inductor; it then decays to zero.

v_L(t) = V_s·e^−t/τ = 24·e^−1/1 = 8.829 V

Answer

v_L = 8.829 V

6.RC & RL transients

Answer: t = 51.08 ms

Initial value, final value, time constant

The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.

v_C(0) = 6 V, v_C(∞) = V_s = 10 V

τ = R·C = 1 kΩ · 100 µF = 100 ms

v_C(t) = 10 + (6 − 10)·e^−t/τ

Solve for the time

7.6 = 10 + (−4)·e^−t/τ → e^−t/τ = (7.6 − 10)/(6 − 10) = 0.6

t = τ·ln((6 − 10)/(7.6 − 10)) = 100·ln(1.667) = 51.08 ms

Answer

t = 51.08 ms

7.Series & parallel resistors

Answer: I_R1 = 1.22 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R₃ + R₄ = 5 + 2 = 7 Ω

R₂ ∥ 7 = 5·7/(5+7) = 2.917 Ω

R_eq = R₁ + 2.917 = 2 + 2.917 = 4.917 Ω

Current from the source

The source sees only R_eq, so Ohm’s law gives the current it delivers. That current flows through R₁.

I_R1 = V₁/R_eq = 6/4.917 = 1.22 A

Answer

I_R1 = 1.22 A

8.Series & parallel resistors

Answer: R_eq = 25.09 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R₅ + R₆ = 5 + 25 = 30 Ω

R₄ ∥ 30 = 8.571 Ω

R₃ + 8.571 = 33.57 Ω

R₂ ∥ 33.57 = 5.09 Ω

R_eq = R₁ + 5.09 = 20 + 5.09 = 25.09 Ω

Answer

R_eq = 25.09 Ω

9.DC-DC converters

Answer: L = 1125 µH

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck V_o = D·V_in, boost V_o = V_in/(1 − D), inverting buck-boost |V_o| = V_in·D/(1 − D). An ideal converter keeps the power: V_in·I_in = V_o·I_o. While S is on the inductor current rises by ΔI_L = V_L·D·T/L, with V_L = V_in − V_o for the buck and V_in for the boost and buck-boost. The output ripple is ΔV_o = ΔI_L/(8fC) for the buck and I_o·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔI_L/2.

Duty cycle

D = 36/48 = 0.75

Inductance

L = 12·0.75/(0.2·40·10³) = 1125 µH

Answer

L = 1125 µH

10.DC-DC converters

Answer: I_o,min = 0.1324 A

Duty cycle

D = 18/24 = 0.75

Ripple current

ΔI_L = 18·0.25/(68·10⁻⁶·250·10³) = 0.2647 A

Boundary load current

I_o,min = ΔI_L/2 = 0.1324 A

Answer

I_o,min = 0.1324 A

Below this current the converter enters discontinuous conduction and V_o rises above D·V_in.

11.Wheatstone bridge & strain gauges

Answer: R_th = 150.4 Ω

Wheatstone bridge: two voltage dividers share one supply V_s. The left divider R₁–R₂ gives V_a = V_s·R₂/(R₁ + R₂) and the right divider R₃–R₄ gives V_b = V_s·R₄/(R₃ + R₄); the output is V_ab = V_a − V_b. The bridge is balanced (V_ab = 0, no current in the meter) when R₁/R₂ = R₃/R₄, that is R₁·R₄ = R₂·R₃. Seen from the output, the bridge is a Thévenin source with R_th = R₁∥R₂ + R₃∥R₄.

Supply shorted

R₁∥R₂ = 1000·60/1060 = 56.6 Ω

R₃∥R₄ = 150·250/400 = 93.75 Ω

Thévenin resistance

R_th = 150.4 Ω

Answer

R_th = 150.4 Ω

12.Wheatstone bridge & strain gauges

Answer: G = 1467

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives V_o ≈ V_s·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give V_s·GF·ε/2, and four (full bridge) give V_s·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Bridge output at full scale

V_o = 2.25 mV

Gain

G = 3.3/0.00225 = 1467

Answer

G = 1467

13.Digital logic: gates, K-maps & flip-flops

Answer: L = 3

Boolean algebra: the rules that simplify expressions are X + X′ = 1 and X·X′ = 0, X + X = X, absorption X + X·Y = X, the combining rule X·Y + X·Y′ = X, X + X′Y = X + Y and the consensus theorem XY + X′Z + YZ = XY + X′Z. De Morgan's laws turn (X·Y)′ into X′ + Y′ and (X + Y)′ into X′·Y′. A Karnaugh map applies these rules graphically: every group of two neighbouring cells is one use of XY + XY′ = X.

Minterms of the expression

A′B′C → m(1)

A′BC → m(3)

A′B′ → m(0, 1)

AC → m(5, 7)

Group and read off

F = C + A′B′

Count the literals

L = 3

Answer

L = 3

14.Digital logic: gates, K-maps & flip-flops

Answer: L = 11

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Prime implicants

The largest groups that can be formed from 1s and Xs.

C′D′, B′CD, AD′, AC′, A′CD, AB′

Minimal cover

F = C′D′ + AD′ + AC′ + A′CD + AB′

L = 11

Answer

L = 11

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