Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 75 is biased by a base resistor RB = 330 kΩ from the supply VCC = 9 V. The collector resistor is RC = 1 kΩ and the emitter is grounded. Take VBE = 0.7 V and assume the transistor is in the active region. Find the collector current IC in mA.
VCC = 9 VRB = 330 kΩRC = 1 kΩβ = 75VBE = 0.7 V
IC = mA
2.Diodes & transistorsHard
An NPN transistor with β = 100 switches a 1 kΩ load resistor connected between VCC = 5 V and its collector. The emitter is grounded. The base is driven from a 5 V logic output through a base resistor RB. Take VBE = 0.7 V and VCE(sat) = 0.2 V. For reliable switching, design for a base current 5 times the minimum needed for saturation. Find RB in kΩ.
The op-amp is ideal and runs from ±15 V supplies; its output saturates at ±12 V. The non-inverting amplifier is driven by a sine wave. Find the largest input amplitude Vin,max (peak value) for which the output does not clip.
R1 = 1 kΩRf = 22 kΩVsat = ±12 V
Vin,max = V
4.Op-amp circuitsHard
Two ideal op-amp stages are connected in cascade: an inverting amplifier (R1, Rf1) followed by a non-inverting amplifier (R2 to ground, Rf2 in the feedback). Both run from ±15 V supplies. Find the overall voltage gain Av = Vout/Vin.
R1 = 4.7 kΩRf1 = 10 kΩR2 = 47 kΩRf2 = 10 kΩ
Av =
5.RC & RL transientsMedium
The inductor carries no current before the switch closes at t = 0. Find the energy W stored in the inductor at t = 25 ms, in mJ.
Vs = 9 VR = 10 ΩL = 100 mHt = 25 ms
W = mJ
6.RC & RL transientsHard
A timer starts charging an uncharged capacitor through a resistor from a 9 V supply at t = 0. It must trigger when the capacitor voltage reaches 5.69 V, exactly 200 ms after the start. With C = 10 µF, find the resistance R needed.
Vs = 9 VVth = 5.69 VT = 200 msC = 10 µF
R = kΩ
7.Series & parallel resistorsMedium
Find the equivalent resistance Req seen by the source V1.
V1 = 18 VR1 = 6 ΩR2 = 12 ΩR3 = 6 ΩR4 = 3 Ω
Req = Ω
8.Series & parallel resistorsHard
Find the equivalent resistance Req seen by the source V1.
A buck converter turns 24 V into 12 V for a 15 Ω load. It switches at 20 kHz with L = 330 µH. Find the peak inductor current Imax.
Vin = 24 VVo = 12 Vf = 20 kHzL = 330 µHR = 15 Ω
Imax = A
10.DC-DC convertersHard
A buck converter turns 36 V into 10.8 V at 20 kHz with L = 150 µH. Find the smallest load current Io,min for which it stays in continuous conduction.
Vin = 36 VVo = 10.8 Vf = 20 kHzL = 150 µH
Io,min = A
11.Wheatstone bridge & strain gaugesMedium
A bridge with four 120 Ω arms is supplied with 6 V. When the sensor R₂ changes, the output reads Vab = 14.93 mV. Find the exact change ΔR of R₂.
Vs = 6 VR = 120 ΩVab = 14.93 mV
ΔR = Ω
12.Wheatstone bridge & strain gaugesHard
A load cell (a full bridge of strain gauges) has a rated output of 1.5 mV/V at its rated load of 200 kg. It is excited with 10 V. Find its output Vo under a load of 100 kg.
Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C) = Σm(2, 4, 5, 7). How many product terms N does it have?
F(A, B, C) = Σm(2, 4, 5, 7)
N =
14.Digital logic: gates, K-maps & flip-flopsHard
A synchronous mod-5 counter counts 0, 1, …, 4 and then returns to 0. It starts at 3. Which count Q (in decimal) does it show after 9 clock pulses?
Q0 = 39N = 5
Q =
3Solutions
1.Diodes & transistors
Answer: IC = 1.886 mA
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Base current
IB = (VCC − VBE)/RB = (9 − 0.7)/330 kΩ = 25.15 µA
Collector current
IC = β·IB = 75·25.15 µA = 1.886 mA
Answer
IC = 1.886 mA
Check: VCE = 7.114 V is well above 0.2 V, so the transistor is indeed active.
2.Diodes & transistors
Answer: RB = 17.92 kΩ
BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.
Collector current in saturation
IC(sat) = (5 − 0.2)/1000 = 4.8 mA
Minimum base current
IB(min) = IC(sat)/β = 4.8/100 = 48 µA
Design base current
IB = 5·48 µA = 240 µA
Base resistor
RB = (5 − 0.7)/IB = 4.3 V/0.24 mA = 17.92 kΩ
Answer
RB = 17.92 kΩ
3.Op-amp circuits
Answer: Vin,max = 0.5217 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain
Av = 1 + Rf/R1 = 1 + 22/1 = 23
Largest input before clipping
Vin,max = Vsat/|Av| = 12/23 = 0.5217 V
Answer
Vin,max = 0.5217 V
4.Op-amp circuits
Answer: Av = −2.58
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain of each stage
A1 = −Rf1/R1 = −10/4.7 = −2.128
A2 = 1 + Rf2/R2 = 1 + 10/47 = 1.213
Overall gain
Av = A1·A2 = −2.128·1.213 = −2.58
Answer
Av = −2.58
5.RC & RL transients
Answer: W = 34.12 mJ
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
τ = L/R = 100 mH / 10 Ω = 10 ms
i(∞) = Vs/R = 9/10 = 0.9 A
Current at the given time
i(t) = 0.9·(1 − e−25/10) = 0.8261 A
Stored energy
W = ½·L·i² = ½·100·0.8261² = 34.12 mJ
Answer
W = 34.12 mJ
6.RC & RL transients
Answer: R = 19.99 kΩ
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Required time constant
5.69 = 9·(1 − e−200/τ) → τ = 200/ln(9/(9 − 5.69))
τ = 200/1 = 199.9 ms
Resistance
kΩ times µF gives milliseconds.
R = τ/C = 199.9/10 = 19.99 kΩ
Answer
R = 19.99 kΩ
7.Series & parallel resistors
Answer: Req = 11.14 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 6 + 3 = 9 Ω
R2 ∥ 9 = 12·9/(12+9) = 5.143 Ω
Req = R1 + 5.143 = 6 + 5.143 = 11.14 Ω
Answer
Req = 11.14 Ω
8.Series & parallel resistors
Answer: Req = 10.22 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 20 + 25 = 45 Ω
R4 ∥ 45 = 11.25 Ω
R3 + 11.25 = 14.25 Ω
R2 ∥ 14.25 = 4.222 Ω
Req = R1 + 4.222 = 6 + 4.222 = 10.22 Ω
Answer
Req = 10.22 Ω
9.DC-DC converters
Answer: Imax = 1.255 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 12/24 = 0.5
Average and ripple current
Io = 12/15 = 0.8 A
ΔIL = VL·D/(L·f) = 12·0.5/(330·10⁻⁶·20·10³) = 0.9091 A
Peak current
Imax = 0.8 + 0.9091/2 = 1.255 A
Answer
Imax = 1.255 A
10.DC-DC converters
Answer: Io,min = 1.26 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 10.8/36 = 0.3
Ripple current
ΔIL = 10.8·0.7/(150·10⁻⁶·20·10³) = 2.52 A
Boundary load current
Io,min = ΔIL/2 = 1.26 A
Answer
Io,min = 1.26 A
Below this current the converter enters discontinuous conduction and Vo rises above D·Vin.
11.Wheatstone bridge & strain gauges
Answer: ΔR = 1.2 Ω
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Node voltage
Va = 3 + 0.01493 = 3.015 V
Solve the divider
R₂ = 120·3.015/(6 − 3.015) = 121.2 Ω
ΔR = 121.2 − 120 = 1.2 Ω
Answer
ΔR = 1.2 Ω
12.Wheatstone bridge & strain gauges
Answer: Vo = 7.5 mV
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Full-scale output
1.5·10 = 15 mV
Output at this load
Vo = 15·100/200 = 7.5 mV
Answer
Vo = 7.5 mV
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 3
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Group the 1s
Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.
AC
AB′
A′BC′
Minimal SOP form
F = AC + AB′ + A′BC′
N = 3
Answer
N = 3
14.Digital logic: gates, K-maps & flip-flops
Answer: Q = 2
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
Full cycles
Every 5 pulses bring the counter back to the same state.