Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 75 is biased by a base resistor RB = 470 kΩ from the supply VCC = 12 V. The collector resistor is RC = 2.2 kΩ and the emitter is grounded. Take VBE = 0.7 V and assume the transistor is in the active region. Find the collector current IC in mA.
VCC = 12 VRB = 470 kΩRC = 2.2 kΩβ = 75VBE = 0.7 V
IC = mA
2.Diodes & transistorsHard
A 12 V Zener regulator has a 220 Ω series resistor. The input can rise to 22 V, and the load may be disconnected. Find the largest power PZ,max the Zener must dissipate.
Vin,max = 22 VVZ = 12 VR = 220 Ω
PZ,max = mW
3.Op-amp circuitsMedium
Choose the feedback resistor Rf that gives this non-inverting amplifier a voltage gain of 15.
R1 = 22 kΩAv = 15
Rf = kΩ
4.Op-amp circuitsHard
Two ideal op-amp stages are connected in cascade: an inverting amplifier (R1, Rf1) followed by a non-inverting amplifier (R2 to ground, Rf2 in the feedback). Both run from ±15 V supplies. The input is Vin = −0.1 V. Find the output voltage Vout.
The inductor carries no current before the switch closes at t = 0. Find the voltage vL across the inductor at t = 1 ms.
Vs = 6 VR = 50 ΩL = 47 mHt = 1 ms
vL = V
6.RC & RL transientsHard
The switch has been closed for a long time, so the circuit is in steady state. At t = 0 the switch opens. Find the current i2 through R2 at t = 150 ms.
Vs = 15 VR1 = 4.7 kΩR2 = 4.7 kΩC = 22 µFt = 150 ms
i2 = mA
7.Series & parallel resistorsMedium
Find the current IR2 through R2.
V1 = 24 VR1 = 3 ΩR2 = 10 ΩR3 = 20 ΩR4 = 4 Ω
IR2 = A
8.Series & parallel resistorsHard
Find the equivalent resistance Req seen by the source V1.
An ideal buck converter turns 36 V into 10.8 V at 100 kHz with L = 22 µH. Find the peak-to-peak inductor ripple current ΔIL.
Vin = 36 VVo = 10.8 Vf = 100 kHzL = 22 µH
ΔIL = A
10.DC-DC convertersHard
An ideal buck converter turns 12 V into 3.6 V for a 50 Ω load at 100 kHz. Find the smallest inductance Lcrit for continuous conduction.
Vin = 12 VVo = 3.6 Vf = 100 kHzR = 50 Ω
Lcrit = µH
11.Wheatstone bridge & strain gaugesMedium
A bridge with four 330 Ω arms is supplied with 6 V. When the sensor R₂ changes, the output reads Vab = 142.9 mV. Find the exact change ΔR of R₂.
Vs = 6 VR = 330 ΩVab = 142.9 mV
ΔR = Ω
12.Wheatstone bridge & strain gaugesHard
A quarter bridge (one active gauge, GF = 2.05) is excited with 5 V. The largest strain to be measured is 600 µε, and it must give 3.3 V at the input of an analogue-to-digital converter. Find the amplifier gain G.
A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = 0, I₁ = 1, I₂ = 0, I₃ = C. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.
I₀ = 0I₁ = 1I₂ = 0I₃ = C
N =
14.Digital logic: gates, K-maps & flip-flopsHard
A ring counter is made of 8 D flip-flops with the last output fed back to the first input, and starts with a single 1. How many different states N does it go through?
n = 8
N =
3Solutions
1.Diodes & transistors
Answer: IC = 1.803 mA
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Check: VCE = 8.033 V is well above 0.2 V, so the transistor is indeed active.
2.Diodes & transistors
Answer: PZ,max = 545.5 mW
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Worst-case Zener current
IZ = 10/220 = 45.45 mA
Zener power
PZ = 12·45.45 = 545.5 mW
Answer
PZ,max = 545.5 mW
3.Op-amp circuits
Answer: Rf = 308 kΩ
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain of a non-inverting amplifier
V₋ = V₊ = Vin, and the current through R₁ also flows through Rf, so Vout = Vin·(1 + Rf/R₁).
Av = 1 + Rf/R1
Rf = (15 − 1)·22 = 308 kΩ
Answer
Rf = 308 kΩ
4.Op-amp circuits
Answer: Vout = 1.5 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain of each stage
A1 = −Rf1/R1 = −100/10 = −10
A2 = 1 + Rf2/R2 = 1 + 1/2 = 1.5
Stage by stage
V1 = −10·(−0.1) = 1 V
Vout = 1.5·1 = 1.5 V
Answer
Vout = 1.5 V
5.RC & RL transients
Answer: vL = 2.071 V
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
τ = L/R = 47 mH / 50 Ω = 0.94 ms
i(∞) = Vs/R = 6/50 = 0.12 A
Inductor voltage
At t = 0 the whole supply voltage appears across the inductor; it then decays to zero.
vL(t) = Vs·e−t/τ = 6·e−1/0.94 = 2.071 V
Answer
vL = 2.071 V
6.RC & RL transients
Answer: i2 = 0.3741 mA
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial capacitor voltage
In steady state the capacitor is an open circuit, so R₁ and R₂ form a voltage divider. The capacitor voltage cannot jump when the switch opens.
vC(0) = 15·4.7/(4.7 + 4.7) = 7.5 V
Time constant after the switch opens
τ = R2·C = 4.7·22 = 103.4 ms
Discharge
vC(t) = 7.5·e−150/103.4 = 1.758 V
i2 = vC/R2 = 1.758/4.7 = 0.3741 mA
Answer
i2 = 0.3741 mA
7.Series & parallel resistors
Answer: IR2 = 1.684 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 20 + 4 = 24 Ω
R2 ∥ 24 = 10·24/(10+24) = 7.059 Ω
Req = R1 + 7.059 = 3 + 7.059 = 10.06 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 24/10.06 = 2.386 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 24 − 2.386·3 = 16.84 V
IR2 = VA/R2 = 16.84/10 = 1.684 A
Answer
IR2 = 1.684 A
8.Series & parallel resistors
Answer: Req = 23.49 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 25 + 4 = 29 Ω
R4 ∥ 29 = 3.515 Ω
R3 + 3.515 = 11.52 Ω
R2 ∥ 11.52 = 3.486 Ω
Req = R1 + 3.486 = 20 + 3.486 = 23.49 Ω
Answer
Req = 23.49 Ω
9.DC-DC converters
Answer: ΔIL = 3.436 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 10.8/36 = 0.3
Inductor voltage during the on-time
While S is on, the inductor sits between Vin and Vo.
VL = 36 − 10.8 = 25.2 V
Ripple current
ΔIL = VL·D/(L·f) = 25.2·0.3/(22·10⁻⁶·100·10³) = 3.436 A
Answer
ΔIL = 3.436 A
10.DC-DC converters
Answer: Lcrit = 175 µH
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 3.6/12 = 0.3
Boundary condition
Set the average inductor current equal to half the ripple current and solve for L.
Lcrit = (1 − D)·R/(2f)
Critical inductance
Lcrit = (1 − 0.3)·50/(2100·10³) = 175 µH
Answer
Lcrit = 175 µH
11.Wheatstone bridge & strain gauges
Answer: ΔR = 33 Ω
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Node voltage
Va = 3 + 0.1429 = 3.143 V
Solve the divider
R₂ = 330·3.143/(6 − 3.143) = 363 Ω
ΔR = 363 − 330 = 33 Ω
Answer
ΔR = 33 Ω
12.Wheatstone bridge & strain gauges
Answer: G = 2146
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Bridge output at full scale
Vo = 1.537 mV
Gain
G = 3.3/0.001537 = 2146
Answer
G = 2146
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 3
Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.
Output expression
F = A′B + ABC
Rows with F = 1
ABC = 010, 011, 111
N = 3
Answer
N = 3
14.Digital logic: gates, K-maps & flip-flops
Answer: N = 8
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.