Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 200 has voltage-divider bias from VCC = 20 V: R₁ = 47 kΩ from VCC to the base and R₂ = 4.7 kΩ from the base to ground. The collector resistor is RC = 2.2 kΩ and the emitter resistor is RE = 1.5 kΩ. Take VBE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector current IC in mA.
A 9.1 V Zener regulator must supply up to 10 mA to a load. The input can drop to 20 V, and the Zener needs at least 2 mA to regulate. Find the largest series resistance Rmax that keeps it regulating.
An ideal boost converter turns 12 V into 24 V for an 8 Ω load. Find the average inductor current IL.
Vin = 12 VVo = 24 VR = 8 Ω
IL = A
10.DC-DC convertersHard
A buck converter turns 36 V into 9 V for an 8 Ω load at 40 kHz, with L = 220 µH and C = 47 µF. Find the peak-to-peak output voltage ripple ΔVo in mV.
Vin = 36 VVo = 9 Vf = 40 kHzL = 220 µHC = 47 µF
ΔVo = mV
11.Wheatstone bridge & strain gaugesMedium
A 350 Ω strain gauge is one arm (R₂) of a bridge with four equal 350 Ω arms and an excitation of 2 V. Find the power Pg dissipated in the gauge, in mW. Self-heating limits the excitation.
Vs = 2 VR = 350 Ω
Pg = mW
12.Wheatstone bridge & strain gaugesHard
A 350 Ω strain gauge with gauge factor 2 is bonded to a steel bar. Under load its resistance rises by 1.05 Ω. Find the strain ε in microstrain (µε).
In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.
F = Σm(0, 3, 4, 5, 9, 10, 13, 14)
1AB = 00, CD = 00
2AB = 00, CD = 01
3AB = 00, CD = 11
4AB = 00, CD = 10
5AB = 01, CD = 00
6AB = 01, CD = 01
7AB = 01, CD = 11
8AB = 01, CD = 10
9AB = 11, CD = 00
10AB = 11, CD = 01
11AB = 11, CD = 11
12AB = 11, CD = 10
13AB = 10, CD = 00
14AB = 10, CD = 01
15AB = 10, CD = 11
16AB = 10, CD = 10
14.Digital logic: gates, K-maps & flip-flopsHard
An 8 kHz clock drives a mod-100 counter. Find the frequency fout of its most significant output, which completes one cycle per counting cycle.
fclk = 8 kHzN = 100
fout = kHz
3Solutions
1.Diodes & transistors
Answer: IC = 0.7314 mA
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Thévenin equivalent of the divider
VTH = 20·4.7/(47 + 4.7) = 1.818 V
RTH = 47·4.7/(47 + 4.7) = 4.273 kΩ
Base current
KVL around the base loop; the emitter current is (β + 1)·IB.
IB = (1.818 − 0.7)/(4.273 + 201·1.5) = 3.657 µA
Collector current
IC = 200·3.657 µA = 0.7314 mA
IE = 201·3.657 µA = 0.735 mA
Answer
IC = 0.7314 mA
2.Diodes & transistors
Answer: Rmax = 908.3 Ω
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Worst-case current
IR = 10 + 2 = 12 mA
Largest resistance
Rmax = 10.9/0.012 = 908.3 Ω
Answer
Rmax = 908.3 Ω
3.Op-amp circuits
Answer: V− = 1.613 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Voltage at the inputs
R₃ and R₄ carry the same current, so they form a voltage divider; feedback makes V₋ = V₊.
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Input currents
V₋ = 0, so each input resistor has its full input voltage across it.
I1 = V1/R1 = 0.2/1 = 0.2 mA
I2 = V2/R2 = −0.5/4.7 = −0.1064 mA
If = I1 + I2 = 0.09362 mA
Answer
If = 0.09362 mA
5.RC & RL transients
Answer: i = 0.2204 A
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial value, final value, time constant
The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.
t = τ·ln((8 − 6)/(7.4 − 6)) = 100·ln(1.429) = 35.67 ms
Answer
t = 35.67 ms
7.Series & parallel resistors
Answer: IR1 = 0.8108 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 3 + 3 = 6 Ω
R2 ∥ 6 = 4·6/(4+6) = 2.4 Ω
Req = R1 + 2.4 = 5 + 2.4 = 7.4 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 6/7.4 = 0.8108 A
Answer
IR1 = 0.8108 A
8.Series & parallel resistors
Answer: IR1 = 1.095 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 20 + 3 = 23 Ω
R4 ∥ 23 = 6.97 Ω
R3 + 6.97 = 36.97 Ω
R2 ∥ 36.97 = 7.871 Ω
Req = R1 + 7.871 = 25 + 7.871 = 32.87 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 36/32.87 = 1.095 A
Answer
IR1 = 1.095 A
9.DC-DC converters
Answer: IL = 6 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 1 − 12/24 = 0.5
Load current
Io = 24/8 = 3 A
Inductor current
IL = Io/(1 − D) = 3/0.5 = 6 A
Answer
IL = 6 A
10.DC-DC converters
Answer: ΔVo = 51 mV
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 9/36 = 0.25
Inductor ripple current
ΔIL = (36 − 9)·0.25/(220·10⁻⁶·40·10³) = 0.767 A
Output ripple
ΔVo = 0.767/(8·40·10³·47·10⁻⁶) = 51 mV
Answer
ΔVo = 51 mV
11.Wheatstone bridge & strain gauges
Answer: Pg = 2.857 mW
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Voltage across the gauge
V = 2/2 = 1 V
Power
Pg = 1²/350 = 2.857 mW
Answer
Pg = 2.857 mW
12.Wheatstone bridge & strain gauges
Answer: ε = 1500 µε
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Relative resistance change
ΔR/R = 1.05/350 = 0.003
Strain
ε = 0.003/2 = 0.0015 = 1500 µε
Answer
ε = 1500 µε
13.Digital logic: gates, K-maps & flip-flops
Answer: AB = 00, CD = 11
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Neighbours of each 1
A 1 with a neighbouring 1 can join a group of two or more.
m3: m2, m1, m7, m11 → 0
The isolated 1
m3 = A′B′CD → AB = 00, CD = 11
Answer
AB = 00, CD = 11
14.Digital logic: gates, K-maps & flip-flops
Answer: fout = 0.08 kHz
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.