Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 120 is biased by a base resistor RB = 470 kΩ from the supply VCC = 10 V. The collector resistor is RC = 1 kΩ and the emitter is grounded. Take VBE = 0.7 V and assume the transistor is in the active region. Find the collector current IC in mA.
VCC = 10 VRB = 470 kΩRC = 1 kΩβ = 120VBE = 0.7 V
IC = mA
2.Diodes & transistorsHard
A diode is modelled as 0.7 V in series with 10 Ω (it conducts above 0.7 V). It is in series with a 470 Ω resistor across a 6 V supply. Find the operating current ID where the diode line meets the load line.
Vs = 6 VR = 470 ΩV0 = 0.7 Vrd = 10 Ω
ID = mA
3.Op-amp circuitsMedium
The op-amp is ideal and runs from ±15 V supplies. Find the output voltage Vout.
Vin = −0.8 VR1 = 22 kΩRf = 100 kΩ
Vout = V
4.Op-amp circuitsHard
Two ideal op-amp stages are connected in cascade: an inverting amplifier (R1, Rf1) followed by a non-inverting amplifier (R2 to ground, Rf2 in the feedback). Both run from ±15 V supplies. Find the overall voltage gain Av = Vout/Vin.
R1 = 2 kΩRf1 = 22 kΩR2 = 47 kΩRf2 = 22 kΩ
Av =
5.RC & RL transientsMedium
The inductor carries no current before the switch closes at t = 0. Find the voltage vL across the inductor at t = 5 ms.
Vs = 12 VR = 15 ΩL = 47 mHt = 5 ms
vL = V
6.RC & RL transientsHard
Just before the switch closes at t = 0, the capacitor holds 8 V with the polarity shown. How long does it take for vC to reach 9.6 V? Find t.
Vs = 10 VR = 4.7 kΩC = 100 µFvC(0) = 8 V
t = ms
7.Series & parallel resistorsMedium
Find the equivalent resistance Req seen by the source V1.
A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = C, I₁ = 0, I₂ = C′, I₃ = 0. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.
I₀ = CI₁ = 0I₂ = C′I₃ = 0
N =
14.Digital logic: gates, K-maps & flip-flopsHard
A synchronous mod-12 counter counts 0, 1, …, 11 and then returns to 0. It starts at 6. Which count Q (in decimal) does it show after 32 clock pulses?
Q0 = 632N = 12
Q =
3Solutions
1.Diodes & transistors
Answer: IC = 2.374 mA
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Check: VCE = 7.626 V is well above 0.2 V, so the transistor is indeed active.
2.Diodes & transistors
Answer: ID = 11.04 mA
LED and diode circuits: a forward-biased LED drops roughly its forward voltage VF (about 2 V for red, 3 V for blue or white), whatever the current. A series resistor sets the current: R = (Vs − n·VF)/I for n LEDs in series. With a more exact diode model V = V₀ + I·rd, the operating point is where the diode line meets the load line I = (Vs − V)/R, so I = (Vs − V₀)/(R + rd).
Combine the two equations
6 = 0.7 + I·(470 + 10)
Operating current
ID = 5.3/480 = 11.04 mA
VD = 0.7 + 0.01104·10 = 0.8104 V
Answer
ID = 11.04 mA
3.Op-amp circuits
Answer: Vout = −4.436 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain of each stage
A1 = −Rf1/R1 = −22/2 = −11
A2 = 1 + Rf2/R2 = 1 + 22/47 = 1.468
Overall gain
Av = A1·A2 = −11·1.468 = −16.15
Answer
Av = −16.15
5.RC & RL transients
Answer: vL = 2.433 V
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
τ = L/R = 47 mH / 15 Ω = 3.133 ms
i(∞) = Vs/R = 12/15 = 0.8 A
Inductor voltage
At t = 0 the whole supply voltage appears across the inductor; it then decays to zero.
vL(t) = Vs·e−t/τ = 12·e−5/3.133 = 2.433 V
Answer
vL = 2.433 V
6.RC & RL transients
Answer: t = 756.4 ms
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial value, final value, time constant
The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.
t = τ·ln((8 − 10)/(9.6 − 10)) = 470·ln(5) = 756.4 ms
Answer
t = 756.4 ms
7.Series & parallel resistors
Answer: Req = 18.44 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 3 + 8 = 11 Ω
R2 ∥ 11 = 5·11/(5+11) = 3.438 Ω
Req = R1 + 3.438 = 15 + 3.438 = 18.44 Ω
Answer
Req = 18.44 Ω
8.Series & parallel resistors
Answer: IR2 = 1.997 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 12 + 15 = 27 Ω
R4 ∥ 27 = 1.862 Ω
R3 + 1.862 = 11.86 Ω
R2 ∥ 11.86 = 1.711 Ω
Req = R1 + 1.711 = 6 + 1.711 = 7.711 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 18/7.711 = 2.334 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 18 − 2.334·6 = 3.995 V
IR2 = VA/R2 = 3.995/2 = 1.997 A
Answer
IR2 = 1.997 A
9.DC-DC converters
Answer: IL = 8 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 1 − 36/48 = 0.25
Load current
Io = 48/8 = 6 A
Inductor current
IL = Io/(1 − D) = 6/0.75 = 8 A
Answer
IL = 8 A
10.DC-DC converters
Answer: Io,min = 0.03491 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 19.2/48 = 0.4
Ripple current
ΔIL = 19.2·0.6/(330·10⁻⁶·500·10³) = 0.06982 A
Boundary load current
Io,min = ΔIL/2 = 0.03491 A
Answer
Io,min = 0.03491 A
Below this current the converter enters discontinuous conduction and Vo rises above D·Vin.
11.Wheatstone bridge & strain gauges
Answer: ΔR = 17.5 Ω
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Node voltage
Va = 5 + 0.122 = 5.122 V
Solve the divider
R₂ = 350·5.122/(10 − 5.122) = 367.5 Ω
ΔR = 367.5 − 350 = 17.5 Ω
Answer
ΔR = 17.5 Ω
12.Wheatstone bridge & strain gauges
Answer: ε = 199.8 µε
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Solve the quarter-bridge equation
ε = 4·0.000256/(2.5·2.05) = 0.0001998
In microstrain
ε = 199.8 µε
Answer
ε = 199.8 µε
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 2
Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.
Output expression
F = A′B′C + AB′C′
Rows with F = 1
ABC = 001, 100
N = 2
Answer
N = 2
14.Digital logic: gates, K-maps & flip-flops
Answer: Q = 2
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
Full cycles
Every 12 pulses bring the counter back to the same state.