Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 150 is biased by a base resistor RB = 820 kΩ from the supply VCC = 12 V. The collector resistor is RC = 1.5 kΩ and the emitter is grounded. Take VBE = 0.7 V and assume the transistor is in the active region. Find the collector–emitter voltage VCE.
A 5.6 V Zener regulator has a 330 Ω series resistor. The input can rise to 16 V, and the load may be disconnected. Find the largest power PZ,max the Zener must dissipate.
Vin,max = 16 VVZ = 5.6 VR = 330 Ω
PZ,max = mW
3.Op-amp circuitsMedium
The op-amp is ideal and runs from ±15 V supplies; its output saturates at ±13 V. The non-inverting amplifier is driven by a sine wave. Find the largest input amplitude Vin,max (peak value) for which the output does not clip.
R1 = 2 kΩRf = 22 kΩVsat = ±13 V
Vin,max = V
4.Op-amp circuitsHard
The summing amplifier uses an ideal op-amp with ±15 V supplies. Find the output voltage Vout.
V1 = 0.3 VV2 = 1 VR1 = 2 kΩR2 = 100 kΩRf = 47 kΩ
Vout = V
5.RC & RL transientsMedium
The source Vₛ charges the capacitor through R₁, and R₂ is connected in parallel with C. The capacitor is uncharged when the switch closes at t = 0. Find the capacitor voltage vC at t = 50 ms.
Vs = 24 VR1 = 10 kΩR2 = 3.3 kΩC = 22 µFt = 50 ms
vC = V
6.RC & RL transientsHard
The switch across R2 has been open for a long time, so the inductor current is steady. At t = 0 the switch closes and shorts out R2. How long after t = 0 does the inductor current reach 0.568 A? Find t.
Vs = 24 VR1 = 33 ΩR2 = 15 ΩL = 47 mH
t = ms
7.Series & parallel resistorsMedium
Find the current IR2 through R2.
V1 = 24 VR1 = 20 ΩR2 = 6 ΩR3 = 12 ΩR4 = 3 Ω
IR2 = A
8.Series & parallel resistorsHard
Find the current IR1 delivered by the source, which flows through R1.
A buck converter turns 9 V into 6.3 V for a 5 Ω load. It switches at 250 kHz with L = 100 µH. Find the peak inductor current Imax.
Vin = 9 VVo = 6.3 Vf = 250 kHzL = 100 µHR = 5 Ω
Imax = A
10.DC-DC convertersHard
A buck converter turns 15 V into 10.5 V at 100 kHz with L = 330 µH. Find the output capacitance C that limits the peak-to-peak output ripple to 100 mV.
A 200 Ω strain gauge is one arm (R₂) of a bridge with four equal 200 Ω arms and an excitation of 10 V. Find the power Pg dissipated in the gauge, in mW. Self-heating limits the excitation.
Vs = 10 VR = 200 Ω
Pg = mW
12.Wheatstone bridge & strain gaugesHard
A quarter bridge (one active gauge, GF = 2.05) is excited with 5 V. The largest strain to be measured is 800 µε, and it must give 10 V at the input of an analogue-to-digital converter. Find the amplifier gain G.
Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C, D) = Σm(0, 3, 4, 7, 8, 11, 12, 13, 14). How many literals L does it contain in total (a primed variable counts as one literal)?
F(A, B, C, D) = Σm(0, 3, 4, 7, 8, 11, 12, 13, 14)
L =
14.Digital logic: gates, K-maps & flip-flopsHard
Find the minimal SOP form of F(A, B, C, D) = Σm(2, 6, 9, 12, 13, 14) + d(1, 8), where d marks the don't-care conditions. How many product terms N does it have?
F(A, B, C, D) = Σm(2, 6, 9, 12, 13, 14) + d(1, 8)
N =
3Solutions
1.Diodes & transistors
Answer: VCE = 8.899 V
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Worst-case Zener current
IZ = 10.4/330 = 31.52 mA
Zener power
PZ = 5.6·31.52 = 176.5 mW
Answer
PZ,max = 176.5 mW
3.Op-amp circuits
Answer: Vin,max = 1.083 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain
Av = 1 + Rf/R1 = 1 + 22/2 = 12
Largest input before clipping
Vin,max = Vsat/|Av| = 13/12 = 1.083 V
Answer
Vin,max = 1.083 V
4.Op-amp circuits
Answer: Vout = −7.52 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Input currents
V₋ = 0, so each input resistor has its full input voltage across it.
I1 = V1/R1 = 0.3/2 = 0.15 mA
I2 = V2/R2 = 1/100 = 0.01 mA
If = I1 + I2 = 0.16 mA
Output voltage
Vout = −Rf·If = −47·0.16 = −7.52 V
Answer
Vout = −7.52 V
5.RC & RL transients
Answer: vC = 3.572 V
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Thévenin equivalent seen by the capacitor
Short the source to find Rth; open the capacitor to find the voltage it will settle at.
Rth = R1 ∥ R2 = 10·3.3/(10 + 3.3) = 2.481 kΩ
vC(∞) = 24·3.3/(10 + 3.3) = 5.955 V
Time constant
τ = Rth·C = 2.481·22 = 54.59 ms
Charging curve
vC(t) = 5.955·(1 − e−50/54.59) = 3.572 V
Answer
vC = 3.572 V
6.RC & RL transients
Answer: t = 0.5064 ms
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial value, final value, time constant
Before t = 0 both resistors are in the loop; afterwards the closed switch bypasses R₂.
i(0) = 24/(33 + 15) = 0.5 A
i(∞) = 24/33 = 0.7273 A
τ = L/R = 47/33 = 1.424 ms
i(t) = 0.7273 + (0.5 − 0.7273)·e−t/τ
Solve for the time
e−t/τ = (0.568 − 0.7273)/(0.5 − 0.7273) = 0.7008
t = 1.424·ln(1.427) = 0.5064 ms
Answer
t = 0.5064 ms
7.Series & parallel resistors
Answer: IR2 = 0.7059 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 12 + 3 = 15 Ω
R2 ∥ 15 = 6·15/(6+15) = 4.286 Ω
Req = R1 + 4.286 = 20 + 4.286 = 24.29 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 24/24.29 = 0.9882 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 24 − 0.9882·20 = 4.235 V
IR2 = VA/R2 = 4.235/6 = 0.7059 A
Answer
IR2 = 0.7059 A
8.Series & parallel resistors
Answer: IR1 = 1.113 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 15 + 30 = 45 Ω
R4 ∥ 45 = 3.673 Ω
R3 + 3.673 = 13.67 Ω
R2 ∥ 13.67 = 4.17 Ω
Req = R1 + 4.17 = 12 + 4.17 = 16.17 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 18/16.17 = 1.113 A
Answer
IR1 = 1.113 A
9.DC-DC converters
Answer: Imax = 1.298 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 6.3/9 = 0.7
Average and ripple current
Io = 6.3/5 = 1.26 A
ΔIL = VL·D/(L·f) = 2.7·0.7/(100·10⁻⁶·250·10³) = 0.0756 A
Peak current
Imax = 1.26 + 0.0756/2 = 1.298 A
Answer
Imax = 1.298 A
10.DC-DC converters
Answer: C = 1.193 µF
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 10.5/15 = 0.7
Inductor ripple current
ΔIL = (15 − 10.5)·0.7/(330·10⁻⁶·100·10³) = 0.09545 A
Capacitance
C = 0.09545/(8·100·10³·100·10⁻³) = 1.193 µF
Answer
C = 1.193 µF
11.Wheatstone bridge & strain gauges
Answer: Pg = 125 mW
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Voltage across the gauge
V = 10/2 = 5 V
Power
Pg = 5²/200 = 125 mW
Answer
Pg = 125 mW
12.Wheatstone bridge & strain gauges
Answer: G = 4878
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Bridge output at full scale
Vo = 2.05 mV
Gain
G = 10/0.00205 = 4878
Answer
G = 4878
13.Digital logic: gates, K-maps & flip-flops
Answer: L = 14
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Group the 1s
Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.
C′D′
B′CD
A′CD
ABD′
ABC′
Minimal SOP form
F = C′D′ + B′CD + A′CD + ABD′ + ABC′
L = 14
Answer
L = 14
14.Digital logic: gates, K-maps & flip-flops
Answer: N = 3
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Prime implicants
The largest groups that can be formed from 1s and Xs.
B′C′D, BCD′, AC′, A′CD′, ABD′
Minimal cover
F = BCD′ + AC′ + A′CD′
N = 3
Answer
N = 3
Another grouping of the same size exists; it has the same number of terms and literals.