Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
A 5.1 V Zener regulator is fed from 15 V through 100 Ω and supplies a 1500 Ω load. Find the Zener current IZ.
Vin = 15 VVZ = 5.1 VR = 100 ΩRL = 1500 Ω
IZ = mA
2.Diodes & transistorsHard
A diode is modelled as 0.65 V in series with 25 Ω (it conducts above 0.65 V). It is in series with a 330 Ω resistor across a 6 V supply. Find the operating current ID where the diode line meets the load line.
Vs = 6 VR = 330 ΩV0 = 0.65 Vrd = 25 Ω
ID = mA
3.Op-amp circuitsMedium
The op-amp is ideal and runs from ±15 V supplies. Find the output voltage Vout.
Vin = 1.1 VR1 = 2 kΩRf = 10 kΩ
Vout = V
4.Op-amp circuitsHard
The op-amp is ideal and runs from ±15 V supplies. The resistor ratios are not matched. Find the output voltage Vout.
A 200 Ω strain gauge is one arm (R₂) of a bridge with four equal 200 Ω arms and an excitation of 2 V. Find the power Pg dissipated in the gauge, in mW. Self-heating limits the excitation.
Vs = 2 VR = 200 Ω
Pg = mW
12.Wheatstone bridge & strain gaugesHard
A bridge with 350 Ω arms is excited with 3 V and has four active gauges, two in tension and two in compression (full bridge). The gauge factor is 2.1 and the strain is 200 µε. Find the bridge output Vo in mV.
A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = C, I₁ = 0, I₂ = 0, I₃ = C. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.
I₀ = CI₁ = 0I₂ = 0I₃ = C
N =
14.Digital logic: gates, K-maps & flip-flopsHard
A 4-bit binary up counter starts at 3 (decimal, Q = 0011). Which count Q (in decimal) does it show after 20 clock pulses?
Q0 = 320n = 4
Q =
3Solutions
1.Diodes & transistors
Answer: IZ = 95.6 mA
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Resistor current
IR = 9.9/100 = 99 mA
Load current
IL = 5.1/1500 = 3.4 mA
Zener current
IZ = 99 − 3.4 = 95.6 mA
Answer
IZ = 95.6 mA
2.Diodes & transistors
Answer: ID = 15.07 mA
LED and diode circuits: a forward-biased LED drops roughly its forward voltage VF (about 2 V for red, 3 V for blue or white), whatever the current. A series resistor sets the current: R = (Vs − n·VF)/I for n LEDs in series. With a more exact diode model V = V₀ + I·rd, the operating point is where the diode line meets the load line I = (Vs − V)/R, so I = (Vs − V₀)/(R + rd).
Combine the two equations
6 = 0.65 + I·(330 + 25)
Operating current
ID = 5.35/355 = 15.07 mA
VD = 0.65 + 0.01507·25 = 1.027 V
Answer
ID = 15.07 mA
3.Op-amp circuits
Answer: Vout = 6.6 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Inverting input follows the input
V₋ = V₊ = 1.1 V
I = V₋/R1 = 1.1/2 = 0.55 mA
Output voltage
The current through R₁ also flows through Rf.
Vout = V₋ + I·Rf = 1.1 + 0.55·10 = 6.6 V
Answer
Vout = 6.6 V
4.Op-amp circuits
Answer: Vout = −5.169 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Voltage at the + input
V₊ = V2·R4/(R3 + R4) = 0.9·2/(10 + 2) = 0.15 V
Superpose the two inputs
With V₂ = 0, V₁ sees an inverting amplifier. With V₁ = 0, V₊ is amplified by the non-inverting gain 1 + R₂/R₁.
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
τ = L/R = 22 mH / 47 Ω = 0.4681 ms
i(∞) = Vs/R = 10/47 = 0.2128 A
Inductor voltage
At t = 0 the whole supply voltage appears across the inductor; it then decays to zero.
vL(t) = Vs·e−t/τ = 10·e−1/0.4681 = 1.181 V
Answer
vL = 1.181 V
6.RC & RL transients
Answer: vC = 10.65 V
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial value, final value, time constant
The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.
vC(0) = 20 V, vC(∞) = Vs = 6 V
τ = R·C = 10 kΩ · 68 µF = 680 ms
vC(t) = 6 + (20 − 6)·e−t/τ
Voltage at the given time
vC(750) = 6 + (14)·e−750/680 = 10.65 V
Answer
vC = 10.65 V
7.Series & parallel resistors
Answer: Req = 28.89 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 12 + 4 = 16 Ω
R2 ∥ 16 = 20·16/(20+16) = 8.889 Ω
Req = R1 + 8.889 = 20 + 8.889 = 28.89 Ω
Answer
Req = 28.89 Ω
8.Series & parallel resistors
Answer: Req = 16.91 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 25 + 30 = 55 Ω
R4 ∥ 55 = 1.93 Ω
R3 + 1.93 = 26.93 Ω
R2 ∥ 26.93 = 4.907 Ω
Req = R1 + 4.907 = 12 + 4.907 = 16.91 Ω
Answer
Req = 16.91 Ω
9.DC-DC converters
Answer: IL = 2.133 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 1 − 12/16 = 0.25
Load current
Io = 16/10 = 1.6 A
Inductor current
IL = Io/(1 − D) = 1.6/0.75 = 2.133 A
Answer
IL = 2.133 A
10.DC-DC converters
Answer: ΔVo = 0.7219 mV
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 3.6/9 = 0.4
Inductor ripple current
ΔIL = (9 − 3.6)·0.4/(68·10⁻⁶·500·10³) = 0.06353 A
Output ripple
ΔVo = 0.06353/(8·500·10³·22·10⁻⁶) = 0.7219 mV
Answer
ΔVo = 0.7219 mV
11.Wheatstone bridge & strain gauges
Answer: Pg = 5 mW
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Voltage across the gauge
V = 2/2 = 1 V
Power
Pg = 1²/200 = 5 mW
Answer
Pg = 5 mW
12.Wheatstone bridge & strain gauges
Answer: Vo = 1.26 mV
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Relative resistance change
ΔR/R = 2.1·200·10⁻⁶ = 0.00042
Bridge output
Vo = Vs·GF·ε = 3·0.00042 = 1.26 mV
Answer
Vo = 1.26 mV
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 2
Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.
Output expression
F = A′B′C + ABC
Rows with F = 1
ABC = 001, 111
N = 2
Answer
N = 2
14.Digital logic: gates, K-maps & flip-flops
Answer: Q = 7
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
Full cycles
Every 16 pulses bring the counter back to the same state.