Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
A 6.2 V Zener regulator is fed from 15 V through 270 Ω and supplies a 2200 Ω load. Find the Zener current IZ.
Vin = 15 VVZ = 6.2 VR = 270 ΩRL = 2200 Ω
IZ = mA
2.Diodes & transistorsHard
An NPN transistor with β = 150 switches a 150 Ω load resistor connected between VCC = 12 V and its collector. The emitter is grounded. The base is driven from a 3.3 V logic output through a base resistor RB. Take VBE = 0.7 V and VCE(sat) = 0.2 V. Find the largest base resistor RB, in kΩ, that still drives the transistor just into saturation.
Choose the feedback resistor Rf that gives this non-inverting amplifier a voltage gain of 25.
R1 = 100 kΩAv = 25
Rf = kΩ
4.Op-amp circuitsHard
The integrator uses an ideal op-amp with ±15 V supplies; its output saturates at ±14 V. The capacitor is uncharged when a constant input Vin = 2.8 V is applied at t = 0. How long after t = 0 does the output reach saturation? Find t.
Vin = 2.8 VR = 2.2 kΩC = 1 µFVsat = ±14 V
t = ms
5.RC & RL transientsMedium
The inductor carries no current before the switch closes at t = 0. Find the energy W stored in the inductor at t = 1 ms, in mJ.
Vs = 6 VR = 33 ΩL = 10 mHt = 1 ms
W = mJ
6.RC & RL transientsHard
The switch has been closed for a long time, so the circuit is in steady state. At t = 0 the switch opens. Find the current i2 through R2 at t = 200 ms.
Vs = 15 VR1 = 2.2 kΩR2 = 2.2 kΩC = 100 µFt = 200 ms
i2 = mA
7.Series & parallel resistorsMedium
Find the current IR2 through R2.
V1 = 24 VR1 = 15 ΩR2 = 10 ΩR3 = 8 ΩR4 = 3 Ω
IR2 = A
8.Series & parallel resistorsHard
Find the equivalent resistance Req seen by the source V1.
An ideal buck converter turns 36 V into 18 V at 25 kHz with L = 220 µH. Find the peak-to-peak inductor ripple current ΔIL.
Vin = 36 VVo = 18 Vf = 25 kHzL = 220 µH
ΔIL = A
10.DC-DC convertersHard
A buck converter turns 9 V into 4.5 V for a 10 Ω load at 250 kHz, with L = 68 µH and C = 220 µF. Find the peak-to-peak output voltage ripple ΔVo in mV.
A bridge has four 1000 Ω arms and Vs = 15 V. The sensor R₂ increases by ΔR = 5 Ω. Using the small-change approximation, find the output Vab in mV.
Vs = 15 VR = 1000 ΩΔR = 5 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
A quarter bridge (one active gauge, GF = 2.1) is excited with 10 V. The largest strain to be measured is 200 µε, and it must give 5 V at the input of an analogue-to-digital converter. Find the amplifier gain G.
Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C, D) = Σm(1, 2, 3, 4, 10, 13, 15). How many literals L does it contain in total (a primed variable counts as one literal)?
F(A, B, C, D) = Σm(1, 2, 3, 4, 10, 13, 15)
L =
14.Digital logic: gates, K-maps & flip-flopsHard
A 4-bit ring counter Q₃Q₂Q₁Q₀ starts at 1000. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀) and Q₃ receives Q₀. Give the state Q = Q₃Q₂Q₁Q₀ as a decimal number after 7 clock edges.
Q₃Q₂Q₁Q₀ = 10007
Q =
3Solutions
1.Diodes & transistors
Answer: IZ = 29.77 mA
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Resistor current
IR = 8.8/270 = 32.59 mA
Load current
IL = 6.2/2200 = 2.818 mA
Zener current
IZ = 32.59 − 2.818 = 29.77 mA
Answer
IZ = 29.77 mA
2.Diodes & transistors
Answer: RB = 4.958 kΩ
BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.
Collector current in saturation
IC(sat) = (12 − 0.2)/150 = 78.67 mA
Minimum base current
IB(min) = IC(sat)/β = 78.67/150 = 524.4 µA
Base resistor
RB = (3.3 − 0.7)/IB = 2.6 V/0.5244 mA = 4.958 kΩ
Answer
RB = 4.958 kΩ
Any smaller base resistor also saturates the transistor; in practice you pick one a few times smaller.
3.Op-amp circuits
Answer: Rf = 2400 kΩ
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain of a non-inverting amplifier
V₋ = V₊ = Vin, and the current through R₁ also flows through Rf, so Vout = Vin·(1 + Rf/R₁).
Av = 1 + Rf/R1
Rf = (25 − 1)·100 = 2400 kΩ
Answer
Rf = 2400 kΩ
4.Op-amp circuits
Answer: t = 11 ms
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Input current and ramp rate
kΩ times µF gives milliseconds.
RC = 2.2 kΩ · 1 µF = 2.2 ms
ramp rate = −Vin/(RC) = −2.8/2.2 = −1.273 V/ms
Time to saturation
|Vin|·t/(RC) = Vsat → t = Vsat·RC/|Vin| = 14·2.2/2.8 = 11 ms
Answer
t = 11 ms
5.RC & RL transients
Answer: W = 0.1533 mJ
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
τ = L/R = 10 mH / 33 Ω = 0.303 ms
i(∞) = Vs/R = 6/33 = 0.1818 A
Current at the given time
i(t) = 0.1818·(1 − e−1/0.303) = 0.1751 A
Stored energy
W = ½·L·i² = ½·10·0.1751² = 0.1533 mJ
Answer
W = 0.1533 mJ
6.RC & RL transients
Answer: i2 = 1.373 mA
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial capacitor voltage
In steady state the capacitor is an open circuit, so R₁ and R₂ form a voltage divider. The capacitor voltage cannot jump when the switch opens.
vC(0) = 15·2.2/(2.2 + 2.2) = 7.5 V
Time constant after the switch opens
τ = R2·C = 2.2·100 = 220 ms
Discharge
vC(t) = 7.5·e−200/220 = 3.022 V
i2 = vC/R2 = 3.022/2.2 = 1.373 mA
Answer
i2 = 1.373 mA
7.Series & parallel resistors
Answer: IR2 = 0.6212 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 8 + 3 = 11 Ω
R2 ∥ 11 = 10·11/(10+11) = 5.238 Ω
Req = R1 + 5.238 = 15 + 5.238 = 20.24 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 24/20.24 = 1.186 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 24 − 1.186·15 = 6.212 V
IR2 = VA/R2 = 6.212/10 = 0.6212 A
Answer
IR2 = 0.6212 A
8.Series & parallel resistors
Answer: Req = 8.629 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 12 + 2 = 14 Ω
R4 ∥ 14 = 5.833 Ω
R3 + 5.833 = 7.833 Ω
R2 ∥ 7.833 = 5.629 Ω
Req = R1 + 5.629 = 3 + 5.629 = 8.629 Ω
Answer
Req = 8.629 Ω
9.DC-DC converters
Answer: ΔIL = 1.636 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 18/36 = 0.5
Inductor voltage during the on-time
While S is on, the inductor sits between Vin and Vo.
VL = 36 − 18 = 18 V
Ripple current
ΔIL = VL·D/(L·f) = 18·0.5/(220·10⁻⁶·25·10³) = 1.636 A
Answer
ΔIL = 1.636 A
10.DC-DC converters
Answer: ΔVo = 0.3008 mV
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 4.5/9 = 0.5
Inductor ripple current
ΔIL = (9 − 4.5)·0.5/(68·10⁻⁶·250·10³) = 0.1324 A
Output ripple
ΔVo = 0.1324/(8·250·10³·220·10⁻⁶) = 0.3008 mV
Answer
ΔVo = 0.3008 mV
11.Wheatstone bridge & strain gauges
Answer: Vab = 18.75 mV
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Relative change
ΔR/R = 5/1000 = 0.005
Linearised output
Vab ≈ 15·0.005/4 = 18.75 mV
Answer
Vab = 18.75 mV
The exact value is 18.7 mV; the approximation is good while ΔR/R is small.
12.Wheatstone bridge & strain gauges
Answer: G = 4762
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Bridge output at full scale
Vo = 1.05 mV
Gain
G = 5/0.00105 = 4762
Answer
G = 4762
13.Digital logic: gates, K-maps & flip-flops
Answer: L = 13
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Group the 1s
Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.
B′CD′
A′B′D
ABD
A′BC′D′
Minimal SOP form
F = B′CD′ + A′B′D + ABD + A′BC′D′
L = 13
Answer
L = 13
14.Digital logic: gates, K-maps & flip-flops
Answer: Q = 1
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.