Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 200 has voltage-divider bias from VCC = 20 V: R₁ = 47 kΩ from VCC to the base and R₂ = 12 kΩ from the base to ground. The collector resistor is RC = 2.7 kΩ and the emitter resistor is RE = 1.5 kΩ. Take VBE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector current IC in mA.
An NPN transistor with β = 200 switches a 680 Ω load resistor connected between VCC = 9 V and its collector. The emitter is grounded. The base is driven from a 5 V logic output through a base resistor RB = 100 kΩ. Take VBE = 0.7 V and VCE(sat) = 0.2 V. Find the collector current IC in mA when the input is high. Decide first whether the transistor is saturated.
The inductor carries a steady current of 2.5 A. At t = 0 the switch closes the loop through R and the source is removed, so the inductor current decays through R. How long does it take for the current to fall to 1.25 A? Find t.
i(0) = 2.5 AR = 15 ΩL = 100 mH
t = ms
6.RC & RL transientsHard
A timer starts charging an uncharged capacitor through a resistor from a 12 V supply at t = 0. It must trigger when the capacitor voltage reaches 9 V, exactly 10 ms after the start. With R = 22 kΩ, find the capacitance C needed.
Vs = 12 VVth = 9 VT = 10 msR = 22 kΩ
C = µF
7.Series & parallel resistorsMedium
Find the current IR2 through R2.
V1 = 18 VR1 = 12 ΩR2 = 6 ΩR3 = 15 ΩR4 = 12 Ω
IR2 = A
8.Series & parallel resistorsHard
Find the current IR1 delivered by the source, which flows through R1.
An ideal inverting buck-boost converter turns 24 V into −16 V at 200 kHz with L = 68 µH. Find the peak-to-peak inductor ripple current ΔIL.
Vin = 24 VVo = −16 Vf = 200 kHzL = 68 µH
ΔIL = A
10.DC-DC convertersHard
An ideal buck-boost converter turns 12 V into −36 V for a 4 Ω load at 25 kHz. The output capacitor is 22 µF. Find the peak-to-peak output voltage ripple ΔVo in mV.
Vin = 12 VVo = −36 Vf = 25 kHzC = 22 µFR = 4 Ω
ΔVo = mV
11.Wheatstone bridge & strain gaugesMedium
A bridge has four 250 Ω arms and Vs = 3 V. The sensor R₂ increases by ΔR = 0.625 Ω. Using the small-change approximation, find the output Vab in mV.
Vs = 3 VR = 250 ΩΔR = 0.625 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
A 120 Ω strain gauge with gauge factor 2 is bonded to a steel bar. Under load its resistance rises by 0.36 Ω. Find the strain ε in microstrain (µε).
Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C) = Σm(4, 6, 7). How many product terms N does it have?
F(A, B, C) = Σm(4, 6, 7)
N =
14.Digital logic: gates, K-maps & flip-flopsHard
A ring counter is made of 4 D flip-flops with the last output fed back to the first input, and starts with a single 1. How many different states N does it go through?
n = 4
N =
3Solutions
1.Diodes & transistors
Answer: IC = 2.165 mA
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Thévenin equivalent of the divider
VTH = 20·12/(47 + 12) = 4.068 V
RTH = 47·12/(47 + 12) = 9.559 kΩ
Base current
KVL around the base loop; the emitter current is (β + 1)·IB.
IB = (4.068 − 0.7)/(9.559 + 201·1.5) = 10.83 µA
Collector current
IC = 200·10.83 µA = 2.165 mA
IE = 201·10.83 µA = 2.176 mA
Answer
IC = 2.165 mA
2.Diodes & transistors
Answer: IC = 8.6 mA
BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.
Base current
IB = (5 − 0.7)/100 kΩ = 43 µA
Saturated or active?
β·IB is smaller than IC(sat), so the transistor stays active.
β·IB = 8.6 mA
IC(sat) = (9 − 0.2)/680 = 12.94 mA
Collector current
IC = β·IB = 8.6 mA
Answer
IC = 8.6 mA
The transistor is active, so the load is not fully switched on.
3.Op-amp circuits
Answer: Vout = 0.3128 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Inverting input follows the input
V₋ = V₊ = 0.1 V
I = V₋/R1 = 0.1/4.7 = 0.02128 mA
Output voltage
The current through R₁ also flows through Rf.
Vout = V₋ + I·Rf = 0.1 + 0.02128·10 = 0.3128 V
Answer
Vout = 0.3128 V
4.Op-amp circuits
Answer: Vout = −1.507 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Input currents
V₋ = 0, so each input resistor has its full input voltage across it.
I1 = V1/R1 = 0.6/10 = 0.06 mA
I2 = V2/R2 = 0.4/47 = 0.008511 mA
If = I1 + I2 = 0.06851 mA
Output voltage
Vout = −Rf·If = −22·0.06851 = −1.507 V
Answer
Vout = −1.507 V
5.RC & RL transients
Answer: t = 4.621 ms
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant
τ = L/R = 100 mH / 15 Ω = 6.667 ms
Solve for the time
1.25 = 2.5·e−t/τ → t = τ·ln(2.5/1.25)
t = 6.667·ln(2) = 4.621 ms
Answer
t = 4.621 ms
6.RC & RL transients
Answer: C = 0.3279 µF
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Required time constant
9 = 12·(1 − e−10/τ) → τ = 10/ln(12/(12 − 9))
τ = 10/1.386 = 7.213 ms
Capacitance
kΩ times µF gives milliseconds.
C = τ/R = 7.213/22 = 0.3279 µF
Answer
C = 0.3279 µF
7.Series & parallel resistors
Answer: IR2 = 0.871 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 15 + 12 = 27 Ω
R2 ∥ 27 = 6·27/(6+27) = 4.909 Ω
Req = R1 + 4.909 = 12 + 4.909 = 16.91 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 18/16.91 = 1.065 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 18 − 1.065·12 = 5.226 V
IR2 = VA/R2 = 5.226/6 = 0.871 A
Answer
IR2 = 0.871 A
8.Series & parallel resistors
Answer: IR1 = 0.2339 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 6 + 15 = 21 Ω
R4 ∥ 21 = 8.75 Ω
R3 + 8.75 = 28.75 Ω
R2 ∥ 28.75 = 13.37 Ω
Req = R1 + 13.37 = 8 + 13.37 = 21.37 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 5/21.37 = 0.2339 A
Answer
IR1 = 0.2339 A
9.DC-DC converters
Answer: ΔIL = 0.7059 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 16/(24 + 16) = 0.4
Inductor voltage during the on-time
While S is on, the inductor sits directly across Vin.
VL = 24 V
Ripple current
ΔIL = VL·D/(L·f) = 24·0.4/(68·10⁻⁶·200·10³) = 0.7059 A
Answer
ΔIL = 0.7059 A
10.DC-DC converters
Answer: ΔVo = 12273 mV
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 36/(12 + 36) = 0.75
Load current
Io = 36/4 = 9 A
Output ripple
ΔVo = 9·0.75/(25·10³·22·10⁻⁶) = 12273 mV
Answer
ΔVo = 12273 mV
11.Wheatstone bridge & strain gauges
Answer: Vab = 1.875 mV
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Relative change
ΔR/R = 0.625/250 = 0.0025
Linearised output
Vab ≈ 3·0.0025/4 = 1.875 mV
Answer
Vab = 1.875 mV
The exact value is 1.873 mV; the approximation is good while ΔR/R is small.
12.Wheatstone bridge & strain gauges
Answer: ε = 1500 µε
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Relative resistance change
ΔR/R = 0.36/120 = 0.003
Strain
ε = 0.003/2 = 0.0015 = 1500 µε
Answer
ε = 1500 µε
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 2
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Group the 1s
Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.
AC′
AB
Minimal SOP form
F = AC′ + AB
N = 2
Answer
N = 2
14.Digital logic: gates, K-maps & flip-flops
Answer: N = 4
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.