Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
4 white LEDs (forward voltage 3 V each) are connected in series with a resistor to a 24 V supply. Find the resistance R that sets the current to 15 mA.
Vs = 24 VVF = 3 Vn = 4I = 15 mA
R = Ω
2.Diodes & transistorsHard
An NPN transistor with β = 100 switches a 150 Ω load resistor connected between VCC = 5 V and its collector. The emitter is grounded. The base is driven from a 5 V logic output through a base resistor RB. Take VBE = 0.7 V and VCE(sat) = 0.2 V. For reliable switching, design for a base current 4 times the minimum needed for saturation. Find RB in kΩ.
Use the Karnaugh map to find the minimal product-of-sums (POS) form of F(A, B, C, D) = Σm(0, 1, 2, 3, 5, 6, 9, 10, 11, 12). How many sum terms (factors) N does it have?
A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.
Q₀ = 0JK
1clock edge 1
2clock edge 2
3clock edge 3
4clock edge 4
5clock edge 5
6clock edge 6
7clock edge 7
8clock edge 8
3Solutions
1.Diodes & transistors
Answer: R = 800 Ω
LED and diode circuits: a forward-biased LED drops roughly its forward voltage VF (about 2 V for red, 3 V for blue or white), whatever the current. A series resistor sets the current: R = (Vs − n·VF)/I for n LEDs in series. With a more exact diode model V = V₀ + I·rd, the operating point is where the diode line meets the load line I = (Vs − V)/R, so I = (Vs − V₀)/(R + rd).
Voltage across the resistor
VR = 24 − 4·3 = 12 V
Resistance
R = 12/0.015 = 800 Ω
Answer
R = 800 Ω
The resistor dissipates 180 mW.
2.Diodes & transistors
Answer: RB = 3.359 kΩ
BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.
Collector current in saturation
IC(sat) = (5 − 0.2)/150 = 32 mA
Minimum base current
IB(min) = IC(sat)/β = 32/100 = 320 µA
Design base current
IB = 4·320 µA = 1280 µA
Base resistor
RB = (5 − 0.7)/IB = 4.3 V/1.28 mA = 3.359 kΩ
Answer
RB = 3.359 kΩ
3.Op-amp circuits
Answer: Rf = 50 kΩ
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain of a non-inverting amplifier
V₋ = V₊ = Vin, and the current through R₁ also flows through Rf, so Vout = Vin·(1 + Rf/R₁).
Av = 1 + Rf/R1
Rf = (6 − 1)·10 = 50 kΩ
Answer
Rf = 50 kΩ
4.Op-amp circuits
Answer: Vout = 1.332 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Input currents
V₋ = 0, so each input resistor has its full input voltage across it.
I1 = V1/R1 = −1.5/47 = −0.03191 mA
I2 = V2/R2 = −1.3/1 = −1.3 mA
If = I1 + I2 = −1.332 mA
Output voltage
Vout = −Rf·If = −1·(−1.332) = 1.332 V
Answer
Vout = 1.332 V
5.RC & RL transients
Answer: W = 0.1373 mJ
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
τ = L/R = 47 mH / 33 Ω = 1.424 ms
i(∞) = Vs/R = 5/33 = 0.1515 A
Current at the given time
i(t) = 0.1515·(1 − e−1/1.424) = 0.07643 A
Stored energy
W = ½·L·i² = ½·47·0.07643² = 0.1373 mJ
Answer
W = 0.1373 mJ
6.RC & RL transients
Answer: vC = 8.692 V
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial value, final value, time constant
The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.
vC(0) = 4 V, vC(∞) = Vs = 24 V
τ = R·C = 6.8 kΩ · 220 µF = 1496 ms
vC(t) = 24 + (4 − 24)·e−t/τ
Voltage at the given time
vC(400) = 24 + (−20)·e−400/1496 = 8.692 V
Answer
vC = 8.692 V
7.Series & parallel resistors
Answer: IR1 = 1.4 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 10 + 6 = 16 Ω
R2 ∥ 16 = 12·16/(12+16) = 6.857 Ω
Req = R1 + 6.857 = 6 + 6.857 = 12.86 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 18/12.86 = 1.4 A
Answer
IR1 = 1.4 A
8.Series & parallel resistors
Answer: Req = 5.792 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 6 + 8 = 14 Ω
R4 ∥ 14 = 2.471 Ω
R3 + 2.471 = 4.471 Ω
R2 ∥ 4.471 = 3.792 Ω
Req = R1 + 3.792 = 2 + 3.792 = 5.792 Ω
Answer
Req = 5.792 Ω
9.DC-DC converters
Answer: ΔIL = 1.909 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 1 − 36/120 = 0.7
Inductor voltage during the on-time
While S is on, the inductor sits directly across Vin.
VL = 36 V
Ripple current
ΔIL = VL·D/(L·f) = 36·0.7/(330·10⁻⁶·40·10³) = 1.909 A
Answer
ΔIL = 1.909 A
10.DC-DC converters
Answer: Io,min = 0.04235 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 4.8/12 = 0.4
Ripple current
ΔIL = 4.8·0.6/(68·10⁻⁶·500·10³) = 0.08471 A
Boundary load current
Io,min = ΔIL/2 = 0.04235 A
Answer
Io,min = 0.04235 A
Below this current the converter enters discontinuous conduction and Vo rises above D·Vin.
11.Wheatstone bridge & strain gauges
Answer: Vab = 12.5 mV
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Relative change
ΔR/R = 5/1000 = 0.005
Linearised output
Vab ≈ 10·0.005/4 = 12.5 mV
Answer
Vab = 12.5 mV
The exact value is 12.47 mV; the approximation is good while ΔR/R is small.
12.Wheatstone bridge & strain gauges
Answer: ε = 1500 µε
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Solve the quarter-bridge equation
ε = 4·0.007875/(10·2.1) = 0.0015
In microstrain
ε = 1500 µε
Answer
ε = 1500 µε
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 5
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Group the 0s
Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.
(B′ + C′ + D′)
(A′ + B′ + D′)
(A′ + B′ + C′)
(A + B′ + C + D)
(A′ + B + C + D)
Minimal POS form
F = (B′ + C′ + D′)(A′ + B′ + D′)(A′ + B′ + C′)(A + B′ + C + D)(A′ + B + C + D)
N = 5
Answer
N = 5
14.Digital logic: gates, K-maps & flip-flops
Answer: clock edge 4
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
Q after every edge
A JK flip-flop: 00 holds, 01 resets (Q = 0), 10 sets (Q = 1), 11 toggles.