Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 200 has voltage-divider bias from VCC = 20 V: R₁ = 33 kΩ from VCC to the base and R₂ = 10 kΩ from the base to ground. The collector resistor is RC = 4.7 kΩ and the emitter resistor is RE = 2.2 kΩ. Take VBE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector–emitter voltage VCE.
A 9.1 V Zener regulator has a 680 Ω series resistor. The input can rise to 22 V, and the load may be disconnected. Find the largest power PZ,max the Zener must dissipate.
Vin,max = 22 VVZ = 9.1 VR = 680 Ω
PZ,max = mW
3.Op-amp circuitsMedium
The op-amp is ideal and runs from ±15 V supplies. Find the output voltage Vout.
Two ideal op-amp stages are connected in cascade: an inverting amplifier (R1, Rf1) followed by a non-inverting amplifier (R2 to ground, Rf2 in the feedback). Both run from ±15 V supplies. The input is Vin = 0.95 V. Find the output voltage Vout.
The inductor carries no current before the switch closes at t = 0. Find the current i at t = 1 ms.
Vs = 15 VR = 15 ΩL = 22 mHt = 1 ms
i = A
6.RC & RL transientsHard
A timer starts charging an uncharged capacitor through a resistor from a 12 V supply at t = 0. It must trigger when the capacitor voltage reaches 9 V, exactly 25 ms after the start. With R = 4.7 kΩ, find the capacitance C needed.
Vs = 12 VVth = 9 VT = 25 msR = 4.7 kΩ
C = µF
7.Series & parallel resistorsMedium
Find the current IR1 delivered by the source, which flows through R1.
An ideal buck converter turns 15 V into 4.5 V at a switching frequency of 20 kHz. Find the inductance L that keeps the peak-to-peak inductor ripple current at 0.6 A.
Vin = 15 VVo = 4.5 Vf = 20 kHzΔIL = 0.6 A
L = µH
10.DC-DC convertersHard
A buck converter turns 36 V into 10.8 V at 100 kHz with L = 220 µH. Find the smallest load current Io,min for which it stays in continuous conduction.
Vin = 36 VVo = 10.8 Vf = 100 kHzL = 220 µH
Io,min = A
11.Wheatstone bridge & strain gaugesMedium
A bridge with four 120 Ω arms is supplied with 3 V. When the sensor R₂ changes, the output reads Vab = 7.46 mV. Find the exact change ΔR of R₂.
Vs = 3 VR = 120 ΩVab = 7.46 mV
ΔR = Ω
12.Wheatstone bridge & strain gaugesHard
A quarter bridge with one active gauge (GF = 2) is excited with 3 V. Under load the output reads 0.375 mV. Find the strain ε in µε.
Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C, D) = Σm(1, 2, 4, 5, 7). How many literals L does it contain in total (a primed variable counts as one literal)?
F(A, B, C, D) = Σm(1, 2, 4, 5, 7)
L =
14.Digital logic: gates, K-maps & flip-flopsHard
A mod-12 counter has to count through 12 different states. What is the minimum number of flip-flops n it needs?
N = 12
n =
3Solutions
1.Diodes & transistors
Answer: VCE = 7.86 V
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Thévenin equivalent of the divider
VTH = 20·10/(33 + 10) = 4.651 V
RTH = 33·10/(33 + 10) = 7.674 kΩ
Base current
KVL around the base loop; the emitter current is (β + 1)·IB.
IB = (4.651 − 0.7)/(7.674 + 201·2.2) = 8.783 µA
Collector current
IC = 200·8.783 µA = 1.757 mA
IE = 201·8.783 µA = 1.765 mA
Collector–emitter voltage
VCE = 20 − 1.757·4.7 − 1.765·2.2 = 7.86 V
Answer
VCE = 7.86 V
2.Diodes & transistors
Answer: PZ,max = 172.6 mW
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Worst-case Zener current
IZ = 12.9/680 = 18.97 mA
Zener power
PZ = 9.1·18.97 = 172.6 mW
Answer
PZ,max = 172.6 mW
3.Op-amp circuits
Answer: Vout = 0.9091 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain of each stage
A1 = −Rf1/R1 = −100/47 = −2.128
A2 = 1 + Rf2/R2 = 1 + 4.7/47 = 1.1
Stage by stage
V1 = −2.128·0.95 = −2.021 V
Vout = 1.1·(−2.021) = −2.223 V
Answer
Vout = −2.223 V
5.RC & RL transients
Answer: i = 0.4943 A
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Required time constant
9 = 12·(1 − e−25/τ) → τ = 25/ln(12/(12 − 9))
τ = 25/1.386 = 18.03 ms
Capacitance
kΩ times µF gives milliseconds.
C = τ/R = 18.03/4.7 = 3.837 µF
Answer
C = 3.837 µF
7.Series & parallel resistors
Answer: IR1 = 2.368 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 6 + 15 = 21 Ω
R2 ∥ 21 = 6·21/(6+21) = 4.667 Ω
Req = R1 + 4.667 = 8 + 4.667 = 12.67 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 30/12.67 = 2.368 A
Answer
IR1 = 2.368 A
8.Series & parallel resistors
Answer: IR2 = 1.288 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 12 + 2 = 14 Ω
R4 ∥ 14 = 5.091 Ω
R3 + 5.091 = 8.091 Ω
R2 ∥ 8.091 = 2.677 Ω
Req = R1 + 2.677 = 2 + 2.677 = 4.677 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 9/4.677 = 1.924 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 9 − 1.924·2 = 5.151 V
IR2 = VA/R2 = 5.151/4 = 1.288 A
Answer
IR2 = 1.288 A
9.DC-DC converters
Answer: L = 262.5 µH
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 4.5/15 = 0.3
Inductance
L = 10.5·0.3/(0.6·20·10³) = 262.5 µH
Answer
L = 262.5 µH
10.DC-DC converters
Answer: Io,min = 0.1718 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 10.8/36 = 0.3
Ripple current
ΔIL = 10.8·0.7/(220·10⁻⁶·100·10³) = 0.3436 A
Boundary load current
Io,min = ΔIL/2 = 0.1718 A
Answer
Io,min = 0.1718 A
Below this current the converter enters discontinuous conduction and Vo rises above D·Vin.
11.Wheatstone bridge & strain gauges
Answer: ΔR = 1.2 Ω
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Node voltage
Va = 1.5 + 0.00746 = 1.507 V
Solve the divider
R₂ = 120·1.507/(3 − 1.507) = 121.2 Ω
ΔR = 121.2 − 120 = 1.2 Ω
Answer
ΔR = 1.2 Ω
12.Wheatstone bridge & strain gauges
Answer: ε = 250 µε
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Solve the quarter-bridge equation
ε = 4·0.000375/(3·2) = 0.00025
In microstrain
ε = 250 µε
Answer
ε = 250 µε
13.Digital logic: gates, K-maps & flip-flops
Answer: L = 13
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Group the 1s
Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.
A′C′D
A′BD
A′BC′
A′B′CD′
Minimal SOP form
F = A′C′D + A′BD + A′BC′ + A′B′CD′
L = 13
Answer
L = 13
14.Digital logic: gates, K-maps & flip-flops
Answer: n = 4
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.