Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

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1Formulas and methods

Diodes & transistors

Diode (constant drop)
VD = 0.7 V when conducting
Active region
VBE = 0.7 V, IC = β·IB, IE = (β + 1)·IB
Fixed bias
IB = (VCC − 0.7)/RB
Divider bias
IB = (VTH − 0.7)/(RTH + (β + 1)RE)
Thévenin of the divider
VTH = VCC·R2/(R1 + R2), RTH = R1∥R2
Collector loop
VCE = VCC − ICRC − IERE
Saturation
IC(sat) = (VCC − VCE(sat))/RC, IB ≥ IC(sat)/β

Op-amp circuits

Inverting amplifier
Vout = −(Rf/Rin)·Vin
Non-inverting amplifier
Vout = (1 + Rf/R1)·Vin
Summing amplifier
Vout = −Rf(V1/R1 + V2/R2)
Ideal op-amp
V+ = V−, Iin = 0

RC & RL transients

Time constant
τ = RC | τ = L/R
Response
x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ
Capacitor at DC
open circuit; vC cannot jump
Inductor at DC
short circuit; iL cannot jump
Settled
t ≈ 5τ

Method

  1. Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
  2. Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
  3. Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
  4. Use x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ.

Series & parallel resistors

Resistors in series
Req = R1 + R2 + …
Resistors in parallel
1/Req = 1/R1 + 1/R2 + …
Two in parallel
Req = R1R2 / (R1 + R2)
Ohm's law
V = I·R
Power
P = V·I = I²R = V²/R

Method

  1. Start at the end of the network furthest from the terminals.
  2. Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
  3. Redraw the circuit after each step.
  4. Repeat until one resistor is left between the terminals.

DC-DC converters

Buck
Vo = D·Vin
Boost
Vo = Vin/(1 − D)
Inverting buck-boost
|Vo| = Vin·D/(1 − D)
Ideal power balance
VinIin = VoIo
Inductor ripple
ΔIL = VL,on·D/(L·f); buck Vin − Vo, boost and buck-boost Vin
Average inductor current
buck Io; boost and buck-boost Io/(1 − D)
Output ripple
buck ΔIL/(8fC); boost and buck-boost Io·D/(fC)
CCM boundary
buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

  1. Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
  2. Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
  3. Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
  4. For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.

Wheatstone bridge & strain gauges

Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε

Method

  1. Treat the bridge as two voltage dividers across the same supply.
  2. For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
  3. For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
  4. For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium
RC​ = 2.2 kΩβ = 150IC​ = ?RE​ = 680 ΩVCC​ = 18 VR1​ = 33 kΩR2​ = 12 kΩ

An NPN transistor with β = 150 has voltage-divider bias from VCC = 18 V: R₁ = 33 kΩ from VCC to the base and R₂ = 12 kΩ from the base to ground. The collector resistor is RC = 2.2 kΩ and the emitter resistor is RE = 680 Ω. Take VBE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector current IC in mA.

VCC = 18 VR1 = 33 kΩR2 = 12 kΩRC = 2.2 kΩRE = 680 Ωβ = 150
IC = mA
2.Diodes & transistorsHard
RC​ = 220 Ωβ = 150VCC​ = 12 V3.3 VRB​ = ?

An NPN transistor with β = 150 switches a 220 Ω load resistor connected between VCC = 12 V and its collector. The emitter is grounded. The base is driven from a 3.3 V logic output through a base resistor RB. Take VBE = 0.7 V and VCE(sat) = 0.2 V. For reliable switching, design for a base current 10 times the minimum needed for saturation. Find RB in kΩ.

VCC = 12 VRC = 220 Ωβ = 150Vin = 3.3 VVBE = 0.7 VVCE(sat) = 0.2 Voverdrive = 10
RB = kΩ
3.Op-amp circuitsMedium
−+Vout​Rf​ = 47 kΩR1​ = 22 kΩVin​

The op-amp is ideal and runs from ±15 V supplies; its output saturates at ±13 V. The non-inverting amplifier is driven by a sine wave. Find the largest input amplitude Vin,max (peak value) for which the output does not clip.

R1 = 22 kΩRf = 47 kΩVsat = ±13 V
Vin,max = V
4.Op-amp circuitsHard
−+Vout​R2​ = 100 kΩV1​ = 0.9 VR1​ = 10 kΩV2​ = 1.2 VR3​ = 1 kΩR4​ = 22 kΩ

The op-amp is ideal and runs from ±15 V supplies. The resistor ratios are not matched. Find the output voltage Vout.

V1 = 0.9 VV2 = 1.2 VR1 = 10 kΩR2 = 100 kΩR3 = 1 kΩR4 = 22 kΩ
Vout = V
5.RC & RL transientsMedium
+−Vs​24 Vt = 0R = 20 ΩL150 mHi(t)

The inductor carries no current before the switch closes at t = 0. How long after the switch closes does the current reach 90% of its final value? Find t.

Vs = 24 VR = 20 ΩL = 150 mH
t = ms
6.RC & RL transientsHard
+−Vs​9 Vt = 0R = 2.2 kΩC47 µF+−vC​vC​(0) = 8 V

Just before the switch closes at t = 0, the capacitor holds 8 V with the polarity shown. Find the capacitor voltage vC at t = 40 ms.

Vs = 9 VR = 2.2 kΩC = 47 µFvC(0) = 8 Vt = 40 ms
vC = V
7.Series & parallel resistorsMedium
R1​ = 5 ΩIR1​R3​ = 15 Ω+−V1​12 VR2​12 ΩAR4​3 ΩB

Find the current IR1 delivered by the source, which flows through R1.

V1 = 12 VR1 = 5 ΩR2 = 12 ΩR3 = 15 ΩR4 = 3 Ω
IR1 = A
8.Series & parallel resistorsHard
R1​ = 10 ΩR3​ = 25 ΩR5​ = 30 Ω+−V1​15 VR2​6 ΩAR4​30 ΩBR6​4 Ω

Find the equivalent resistance Req seen by the source V1.

V1 = 15 VR1 = 10 ΩR2 = 6 ΩR3 = 25 ΩR4 = 30 ΩR5 = 30 ΩR6 = 4 Ω
Req = Ω
9.DC-DC convertersMedium
+−48 VLSCR = 5 Ω+−80 V

An ideal boost converter turns 48 V into 80 V for a 5 Ω load. Find the average inductor current IL.

Vin​ = 48 VVo​ = 80 VR = 5 Ω
IL = A
10.DC-DC convertersHard
+−9 VLSC = 470 µFR = 12 Ω+−36 V

An ideal boost converter turns 9 V into 36 V for a 12 Ω load at 100 kHz. The output capacitor is 470 µF. Find the peak-to-peak output voltage ripple ΔVo in mV.

Vin​ = 9 VVo​ = 36 Vf = 100 kHzC = 470 µFR = 12 Ω
ΔVo = mV
11.Wheatstone bridge & strain gaugesMedium
+−15 VR1​ = 50 ΩR2​ = 1000 ΩR3​ = 50 ΩR4​ = 250 ΩabGRg​ = 20 Ω

A galvanometer with a resistance of 20 Ω is connected between a and b of the bridge shown (Vs = 15 V). Find the galvanometer current Ig from a to b, in µA.

Vs = 15 VR1 = 50 ΩR2 = 1000 ΩR3 = 50 ΩR4 = 250 ΩRg = 20 Ω
Ig = µA
12.Wheatstone bridge & strain gaugesHard
+−10 V350 Ω − ΔR350 Ω + ΔR350 Ω350 Ωab+−Vo​ = ?

A bridge with 350 Ω arms is excited with 10 V and has two active gauges in adjacent arms, one in tension and one in compression (half bridge). The gauge factor is 2.12 and the strain is 800 µε. Find the bridge output Vo in mV.

Vs = 10 VGF = 2.12ε = 800 µε
Vo = mV
13.Digital logic: gates, K-maps & flip-flopsMedium
ABC00011110011011031204051716

Use the Karnaugh map to find the minimal product-of-sums (POS) form of F(A, B, C) = Σm(0, 1, 2, 6, 7). How many sum terms (factors) N does it have?

F(A, B, C) = Σm(0, 1, 2, 6, 7)
N =
14.Digital logic: gates, K-maps & flip-flopsHard
TQ0​Q0​TQ1​Q1​TQ2​Q2​TQ3​Q3​TQ4​Q4​TQ5​Q5​CLK

A 6-bit ripple (asynchronous) counter is built from flip-flops with a propagation delay of 8 ns each. All outputs must have settled before the next clock edge. Find the maximum clock frequency fmax.

n = 6tpd = 8 ns
fmax = MHz

3Solutions

1.Diodes & transistors

Answer: IC = 5.517 mA

BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.

Thévenin equivalent of the divider

VTH = 18·12/(33 + 12) = 4.8 V
RTH = 33·12/(33 + 12) = 8.8 kΩ

Base current

KVL around the base loop; the emitter current is (β + 1)·IB.

IB = (4.8 − 0.7)/(8.8 + 151·0.68) = 36.78 µA

Collector current

IC = 150·36.78 µA = 5.517 mA
IE = 151·36.78 µA = 5.553 mA

Answer

IC = 5.517 mA
2.Diodes & transistors

Answer: RB = 0.7271 kΩ

BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.

Collector current in saturation

IC(sat) = (12 − 0.2)/220 = 53.64 mA

Minimum base current

IB(min) = IC(sat)/β = 53.64/150 = 357.6 µA

Design base current

IB = 10·357.6 µA = 3576 µA

Base resistor

RB = (3.3 − 0.7)/IB = 2.6 V/3.576 mA = 0.7271 kΩ

Answer

RB = 0.7271 kΩ
3.Op-amp circuits

Answer: Vin,max = 4.145 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Gain

Av = 1 + Rf/R1 = 1 + 47/22 = 3.136

Largest input before clipping

Vin,max = Vsat/|Av| = 13/3.136 = 4.145 V

Answer

Vin,max = 4.145 V
4.Op-amp circuits

Answer: Vout = 3.626 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Voltage at the + input

V₊ = V2·R4/(R3 + R4) = 1.2·22/(1 + 22) = 1.148 V

Superpose the two inputs

With V₂ = 0, V₁ sees an inverting amplifier. With V₁ = 0, V₊ is amplified by the non-inverting gain 1 + R₂/R₁.

Vout = −(100/10)·0.9 + (1 + 100/10)·1.148 = −9 + 12.63 = 3.626 V

Answer

Vout = 3.626 V
5.RC & RL transients

Answer: t = 17.27 ms

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Time constant and final current

Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.

τ = L/R = 150 mH / 20 Ω = 7.5 ms
i(∞) = Vs/R = 24/20 = 1.2 A

Solve for the time

0.9 = 1 − e−t/τ → t = −τ·ln(1 − 0.9)
t = −7.5·ln(0.1) = 17.27 ms

Answer

t = 17.27 ms
6.RC & RL transients

Answer: vC = 8.321 V

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Initial value, final value, time constant

The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.

vC(0) = 8 V, vC(∞) = Vs = 9 V
τ = R·C = 2.2 kΩ · 47 µF = 103.4 ms
vC(t) = 9 + (8 − 9)·e−t/τ

Voltage at the given time

vC(40) = 9 + (−1)·e−40/103.4 = 8.321 V

Answer

vC = 8.321 V
7.Series & parallel resistors

Answer: IR1 = 0.9836 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 5 ΩR3​ = 15 Ω+−V1​12 VR2​12 ΩAR4​3 ΩB

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R3 + R4 = 15 + 3 = 18 Ω
R2 ∥ 18 = 12·18/(12+18) = 7.2 Ω
Req = R1 + 7.2 = 5 + 7.2 = 12.2 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 12/12.2 = 0.9836 A

Answer

IR1 = 0.9836 A
8.Series & parallel resistors

Answer: Req = 15.23 Ω

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 10 ΩR3​ = 25 ΩR5​ = 30 Ω+−V1​15 VR2​6 ΩAR4​30 ΩBR6​4 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R5 + R6 = 30 + 4 = 34 Ω
R4 ∥ 34 = 15.94 Ω
R3 + 15.94 = 40.94 Ω
R2 ∥ 40.94 = 5.233 Ω
Req = R1 + 5.233 = 10 + 5.233 = 15.23 Ω

Answer

Req = 15.23 Ω
9.DC-DC converters

Answer: IL = 26.67 A

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 1 − 48/80 = 0.4

Load current

Io = 80/5 = 16 A

Inductor current

IL = Io/(1 − D) = 16/0.6 = 26.67 A

Answer

IL = 26.67 A
10.DC-DC converters

Answer: ΔVo = 47.87 mV

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 1 − 9/36 = 0.75

Load current

Io = 36/12 = 3 A

Output ripple

ΔVo = 3·0.75/(100·10³·470·10⁻⁶) = 47.87 mV

Answer

ΔVo = 47.87 mV
11.Wheatstone bridge & strain gauges

Answer: Ig = 16340 µA

Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.

Thévenin voltage

Vth = 15·(1000/1050 − 250/300) = 1.786 V

Thévenin resistance

Rth = R₁∥R₂ + R₃∥R₄ = 89.29 Ω

Galvanometer current

Ig = 1.786/(89.29 + 20) = 16340 µA

Answer

Ig = 16340 µA
12.Wheatstone bridge & strain gauges

Answer: Vo = 8.48 mV

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Relative resistance change

ΔR/R = 2.12·800·10⁻⁶ = 0.001696

Bridge output

Vo = Vs·GF·ε/2 = 10·0.001696/2 = 8.48 mV

Answer

Vo = 8.48 mV
13.Digital logic: gates, K-maps & flip-flops

Answer: N = 2

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

ABC00011110011011031204051716

Group the 0s

Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.

(A′ + B)
(A + B′ + C′)

Minimal POS form

F = (A′ + B)(A + B′ + C′)
N = 2

Answer

N = 2
14.Digital logic: gates, K-maps & flip-flops

Answer: fmax = 20.83 MHz

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Worst-case settling time

T = 6·8 ns = 48 ns

Maximum frequency

fmax = 1/48 ns = 20.83 MHz

Answer

fmax = 20.83 MHz

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