Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
A 12 V Zener regulator is fed from 18 V through 220 Ω and supplies a 1500 Ω load. Find the Zener current IZ.
Vin = 18 VVZ = 12 VR = 220 ΩRL = 1500 Ω
IZ = mA
2.Diodes & transistorsHard
A 5.1 V Zener regulator has a 220 Ω series resistor. The input can rise to 30 V, and the load may be disconnected. Find the largest power PZ,max the Zener must dissipate.
Vin,max = 30 VVZ = 5.1 VR = 220 Ω
PZ,max = mW
3.Op-amp circuitsMedium
The op-amp is ideal and runs from ±15 V supplies; its output saturates at ±13 V. The non-inverting amplifier is driven by a sine wave. Find the largest input amplitude Vin,max (peak value) for which the output does not clip.
R1 = 47 kΩRf = 100 kΩVsat = ±13 V
Vin,max = V
4.Op-amp circuitsHard
Two ideal op-amp stages are connected in cascade: an inverting amplifier (R1, Rf1) followed by a non-inverting amplifier (R2 to ground, Rf2 in the feedback). Both run from ±15 V supplies. The input is Vin = −0.7 V. Find the output voltage Vout.
The source Vₛ charges the capacitor through R₁, and R₂ is connected in parallel with C. The capacitor is uncharged when the switch closes at t = 0. Find the time constant τ of the circuit after the switch closes.
Vs = 6 VR1 = 1 kΩR2 = 6.8 kΩC = 47 µF
τ = ms
6.RC & RL transientsHard
A timer starts charging an uncharged capacitor through a resistor from a 12 V supply at t = 0. It must trigger when the capacitor voltage reaches 9 V, exactly 250 ms after the start. With R = 10 kΩ, find the capacitance C needed.
Vs = 12 VVth = 9 VT = 250 msR = 10 kΩ
C = µF
7.Series & parallel resistorsMedium
Find the equivalent resistance Req seen by the source V1.
V1 = 12 VR1 = 8 ΩR2 = 6 ΩR3 = 12 ΩR4 = 10 Ω
Req = Ω
8.Series & parallel resistorsHard
Find the current IR1 delivered by the source, which flows through R1.
An ideal buck converter turns 15 V into 4.5 V at 250 kHz with L = 33 µH. Find the peak-to-peak inductor ripple current ΔIL.
Vin = 15 VVo = 4.5 Vf = 250 kHzL = 33 µH
ΔIL = A
10.DC-DC convertersHard
An ideal buck converter turns 12 V into 6 V for a 10 Ω load at 20 kHz. Find the smallest inductance Lcrit for continuous conduction.
Vin = 12 VVo = 6 Vf = 20 kHzR = 10 Ω
Lcrit = µH
11.Wheatstone bridge & strain gaugesMedium
A 330 Ω strain gauge is one arm (R₂) of a bridge with four equal 330 Ω arms and an excitation of 5 V. Find the power Pg dissipated in the gauge, in mW. Self-heating limits the excitation.
Vs = 5 VR = 330 Ω
Pg = mW
12.Wheatstone bridge & strain gaugesHard
A load cell (a full bridge of strain gauges) has a rated output of 2.5 mV/V at its rated load of 500 kg. It is excited with 5 V. Find its output Vo under a load of 400 kg.
Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C, D) = Σm(1, 6, 7, 9, 10). How many product terms N does it have?
F(A, B, C, D) = Σm(1, 6, 7, 9, 10)
N =
14.Digital logic: gates, K-maps & flip-flopsHard
A 4-bit Johnson counter Q₃Q₂Q₁Q₀ starts at 0000. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀) and Q₃ receives the inverse of Q₀. Give the state Q = Q₃Q₂Q₁Q₀ as a decimal number after 3 clock edges.
Q₃Q₂Q₁Q₀ = 00003
Q =
3Solutions
1.Diodes & transistors
Answer: IZ = 19.27 mA
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Resistor current
IR = 6/220 = 27.27 mA
Load current
IL = 12/1500 = 8 mA
Zener current
IZ = 27.27 − 8 = 19.27 mA
Answer
IZ = 19.27 mA
2.Diodes & transistors
Answer: PZ,max = 577.2 mW
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Worst-case Zener current
IZ = 24.9/220 = 113.2 mA
Zener power
PZ = 5.1·113.2 = 577.2 mW
Answer
PZ,max = 577.2 mW
3.Op-amp circuits
Answer: Vin,max = 4.156 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain
Av = 1 + Rf/R1 = 1 + 100/47 = 3.128
Largest input before clipping
Vin,max = Vsat/|Av| = 13/3.128 = 4.156 V
Answer
Vin,max = 4.156 V
4.Op-amp circuits
Answer: Vout = 4.2 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain of each stage
A1 = −Rf1/R1 = −10/2 = −5
A2 = 1 + Rf2/R2 = 1 + 2/10 = 1.2
Stage by stage
V1 = −5·(−0.7) = 3.5 V
Vout = 1.2·3.5 = 4.2 V
Answer
Vout = 4.2 V
5.RC & RL transients
Answer: τ = 40.97 ms
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Thévenin equivalent seen by the capacitor
Short the source to find Rth; open the capacitor to find the voltage it will settle at.
Rth = R1 ∥ R2 = 1·6.8/(1 + 6.8) = 0.8718 kΩ
vC(∞) = 6·6.8/(1 + 6.8) = 5.231 V
Time constant
τ = Rth·C = 0.8718·47 = 40.97 ms
Answer
τ = 40.97 ms
6.RC & RL transients
Answer: C = 18.03 µF
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Required time constant
9 = 12·(1 − e−250/τ) → τ = 250/ln(12/(12 − 9))
τ = 250/1.386 = 180.3 ms
Capacitance
kΩ times µF gives milliseconds.
C = τ/R = 180.3/10 = 18.03 µF
Answer
C = 18.03 µF
7.Series & parallel resistors
Answer: Req = 12.71 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 12 + 10 = 22 Ω
R2 ∥ 22 = 6·22/(6+22) = 4.714 Ω
Req = R1 + 4.714 = 8 + 4.714 = 12.71 Ω
Answer
Req = 12.71 Ω
8.Series & parallel resistors
Answer: IR1 = 0.3092 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 12 + 20 = 32 Ω
R4 ∥ 32 = 2.743 Ω
R3 + 2.743 = 17.74 Ω
R2 ∥ 17.74 = 9.402 Ω
Req = R1 + 9.402 = 10 + 9.402 = 19.4 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 6/19.4 = 0.3092 A
Answer
IR1 = 0.3092 A
9.DC-DC converters
Answer: ΔIL = 0.3818 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 4.5/15 = 0.3
Inductor voltage during the on-time
While S is on, the inductor sits between Vin and Vo.
VL = 15 − 4.5 = 10.5 V
Ripple current
ΔIL = VL·D/(L·f) = 10.5·0.3/(33·10⁻⁶·250·10³) = 0.3818 A
Answer
ΔIL = 0.3818 A
10.DC-DC converters
Answer: Lcrit = 125 µH
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 6/12 = 0.5
Boundary condition
Set the average inductor current equal to half the ripple current and solve for L.
Lcrit = (1 − D)·R/(2f)
Critical inductance
Lcrit = (1 − 0.5)·10/(220·10³) = 125 µH
Answer
Lcrit = 125 µH
11.Wheatstone bridge & strain gauges
Answer: Pg = 18.94 mW
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Voltage across the gauge
V = 5/2 = 2.5 V
Power
Pg = 2.5²/330 = 18.94 mW
Answer
Pg = 18.94 mW
12.Wheatstone bridge & strain gauges
Answer: Vo = 10 mV
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Full-scale output
2.5·5 = 12.5 mV
Output at this load
Vo = 12.5·400/500 = 10 mV
Answer
Vo = 10 mV
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 3
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Group the 1s
Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.
B′C′D
A′BC
AB′CD′
Minimal SOP form
F = B′C′D + A′BC + AB′CD′
N = 3
Answer
N = 3
14.Digital logic: gates, K-maps & flip-flops
Answer: Q = 14
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.