Digital logic: gates, K-maps & flip-flops worksheet with answers

The propagation delay of every gate is written under it. Find the worst-case propagation delay t_pd from the inputs to the output F.

The inputs of the logic circuit are A = 1, B = 0 and C = 0. Exactly one of its gates has the output 0. Click that gate.

1. 1N1
2. 2G1
3. 3G2

In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.

1. 1AB = 00, CD = 00
2. 2AB = 00, CD = 01
3. 3AB = 00, CD = 11
4. 4AB = 00, CD = 10
5. 5AB = 01, CD = 00
6. 6AB = 01, CD = 01
7. 7AB = 01, CD = 11
8. 8AB = 01, CD = 10
9. 9AB = 11, CD = 00
10. 10AB = 11, CD = 01
11. 11AB = 11, CD = 11
12. 12AB = 11, CD = 10
13. 13AB = 10, CD = 00
14. 14AB = 10, CD = 01
15. 15AB = 10, CD = 11
16. 16AB = 10, CD = 10

Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C, D) = Σm(2, 3, 4, 5, 6, 9, 10, 13, 15). How many literals L does it contain in total (a primed variable counts as one literal)?

A 3-bit ripple (asynchronous) counter is built from flip-flops with a propagation delay of 25 ns each. All outputs must have settled before the next clock edge. Find the maximum clock frequency f_max.

A 4-bit binary up counter starts at 2 (decimal, Q = 0010). Which count Q (in decimal) does it show after 39 clock pulses?