Digital logic: gates, K-maps & flip-flops worksheet with answers

The propagation delay of every gate is written under it. Find the worst-case propagation delay t_pd from the inputs to the output F.

For the logic circuit shown, how many of the 8 combinations of the inputs A, B and C give the output F = 1? Find N.

In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.

1. 1AB = 00, CD = 00
2. 2AB = 00, CD = 01
3. 3AB = 00, CD = 11
4. 4AB = 00, CD = 10
5. 5AB = 01, CD = 00
6. 6AB = 01, CD = 01
7. 7AB = 01, CD = 11
8. 8AB = 01, CD = 10
9. 9AB = 11, CD = 00
10. 10AB = 11, CD = 01
11. 11AB = 11, CD = 11
12. 12AB = 11, CD = 10
13. 13AB = 10, CD = 00
14. 14AB = 10, CD = 01
15. 15AB = 10, CD = 11
16. 16AB = 10, CD = 10

Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C, D) = Σm(0, 1, 2, 4, 6, 7, 8, 10). How many product terms N does it have?

A 4-bit ring counter Q₃Q₂Q₁Q₀ starts at 1001. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀) and Q₃ receives Q₀. Give the state Q = Q₃Q₂Q₁Q₀ as a decimal number after 3 clock edges.

A 4-bit ring counter Q₃Q₂Q₁Q₀ starts at 1100. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀) and Q₃ receives Q₀. Give the state Q = Q₃Q₂Q₁Q₀ as a decimal number after 4 clock edges.