The propagation delay of every gate is written under it. Find the worst-case propagation delay tpd from the inputs to the output F.
Digital logic: gates, K-maps & flip-flops worksheet with answers
The inputs of the logic circuit are A = 1, B = 1 and C = 1. Exactly one of its gates has the output 0. Click that gate.
- 1G1
- 2G2
- 3G3
In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.
- 1AB = 00, CD = 00
- 2AB = 00, CD = 01
- 3AB = 00, CD = 11
- 4AB = 00, CD = 10
- 5AB = 01, CD = 00
- 6AB = 01, CD = 01
- 7AB = 01, CD = 11
- 8AB = 01, CD = 10
- 9AB = 11, CD = 00
- 10AB = 11, CD = 01
- 11AB = 11, CD = 11
- 12AB = 11, CD = 10
- 13AB = 10, CD = 00
- 14AB = 10, CD = 01
- 15AB = 10, CD = 11
- 16AB = 10, CD = 10
A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = 1, I₁ = 1, I₂ = 0, I₃ = C′. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.
Find the minimal SOP form of F(A, B, C, D) = Σm(1, 2, 13, 14) + d(5, 7, 8, 11), where d marks the don't-care conditions. How many literals L does it contain?
A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.
- 1clock edge 1
- 2clock edge 2
- 3clock edge 3
- 4clock edge 4
- 5clock edge 5
- 6clock edge 6
- 7clock edge 7
Answer key
- 1. tpd = 12 ns
- 2. G2
- 3. AB = 11, CD = 00
- 4. N = 5
- 5. L = 14
- 6. clock edge 6
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