Digital logic: gates, K-maps & flip-flops worksheet with answers

The inputs of the logic circuit are A = 1, B = 0 and C = 0. Exactly one of its gates has the output 0. Click that gate.

1. 1G1
2. 2G2
3. 3G3

The propagation delay of every gate is written under it. Find the worst-case propagation delay t_pd from the inputs to the output F.

In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.

1. 1AB = 00, CD = 00
2. 2AB = 00, CD = 01
3. 3AB = 00, CD = 11
4. 4AB = 00, CD = 10
5. 5AB = 01, CD = 00
6. 6AB = 01, CD = 01
7. 7AB = 01, CD = 11
8. 8AB = 01, CD = 10
9. 9AB = 11, CD = 00
10. 10AB = 11, CD = 01
11. 11AB = 11, CD = 11
12. 12AB = 11, CD = 10
13. 13AB = 10, CD = 00
14. 14AB = 10, CD = 01
15. 15AB = 10, CD = 11
16. 16AB = 10, CD = 10

Simplify F = AC′ + A′B + BC to its minimal sum-of-products form. How many literals L does the simplified expression contain?

A 4-bit shift register Q₃Q₂Q₁Q₀ holds 0011. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀, Q₀ is lost) and the serial input enters Q₃. The serial input is 0, 0, 1, 1, 1 at the 5 edges. Give the final state Q = Q₃Q₂Q₁Q₀ as a decimal number.

A positive-edge-triggered T flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.

1. 1clock edge 1
2. 2clock edge 2
3. 3clock edge 3
4. 4clock edge 4
5. 5clock edge 5
6. 6clock edge 6
7. 7clock edge 7
8. 8clock edge 8