Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

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1Formulas and methods

Number systems

Place values: binary 2^k, octal 8^k, hex 16^k
To decimal: Σ d_k·b^k
From decimal: divide by the base, read the remainders bottom-up
Hex ↔ binary: one hex digit = 4 bits
Two’s complement: invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates: A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules: X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan: (X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order: 00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells: loses k variables
4-to-1 multiplexer: F = A′B′I₀ + A′BI₁ + AB′I₂ + ABI₃
Flip-flops: D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters: n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; f_out = f_clk/N
Ripple counter: f_max = 1/(n·t_pd)
Ring and Johnson counters: n and 2n states

Method

For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion: f_s > 2·f_max, f_N = f_s/2
Alias frequency: f_a = |f − k·f_s|, k = round(f/f_s)
Step size: 1 LSB = V_FSR/2ᴺ
Quantisation error (rounding): ±½ LSB
Truncating ADC code: D = ⌊V_in/LSB⌋
Bits for a resolution r: 2ᴺ ≥ span/r
Ideal SQNR, full-scale sine: SQNR = 6.02·N + 1.76 dB
Data rate: channels × f_s × N bit/s
Multiplexed ADC: f_s = 1/(n·(t_c + t_set))
UART: T_b = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider: baud = f_clk/(16·D)

Method

Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
For sampling questions, compare each frequency with f_s/2; a higher frequency appears at f_a = |f − k·f_s| with the nearest multiple of f_s.
For resolution questions, find 1 LSB = V_FSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium

The 8-bit pattern 1000 0011 stores a signed integer in two's complement. What is its value N in decimal?

1000 00118 bit

N =

2.Number systemsHard

Set the bits to the 8-bit result of 1010 1010 XOR 0010 1100. What is the result's value R in decimal?

1010 1010XOR0010 1100

R =

3.Digital logic: gates, K-maps & flip-flopsMedium

Simplify F = ABC + A′C + A′B′C′ to its minimal sum-of-products form. How many literals L does the simplified expression contain?

F = ABC + A′C + A′B′C′

L =

4.Digital logic: gates, K-maps & flip-flopsHard

A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown at 6 rising clock edges. How many times N does Q change state?

Q₀ = 0JK

N =

5.Data acquisition & samplingMedium

A 12-bit ADC with an input range of 0 to 2.5 V truncates: its output code is ⌊V_in/LSB⌋ with 1 LSB = V_FSR/2ᴺ. Find the decimal output code D for an input of 1.539 V.

N = 12V_FSR = 2.5 VV_in = 1.539 V

D =

6.Data acquisition & samplingHard

A microcontroller with a 4 MHz clock sets its UART baud rate as f_clk/(16·D), with D a whole number rounded to the nearest value. The target is 115200 baud. Find the percentage error of the real baud rate (positive when it is too fast).

f_clk = 4 MHztarget = 115200 Bd

e = %

3Solutions

1.Number systems

Answer: N = −125

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Add the place values

The other bits keep their normal positive values.

−128 + 2 + 1 = −125

Answer

N = −125

2.Number systems

Answer: R = 134

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Bit by bit

XOR gives 1 where the two bits differ.

1010 1010

XOR 0010 1100

= 1000 0110

Value of the result

1000 0110₂ = 134

Answer

R = 134

3.Digital logic: gates, K-maps & flip-flops

Answer: L = 4

Boolean algebra: the rules that simplify expressions are X + X′ = 1 and X·X′ = 0, X + X = X, absorption X + X·Y = X, the combining rule X·Y + X·Y′ = X, X + X′Y = X + Y and the consensus theorem XY + X′Z + YZ = XY + X′Z. De Morgan's laws turn (X·Y)′ into X′ + Y′ and (X + Y)′ into X′·Y′. A Karnaugh map applies these rules graphically: every group of two neighbouring cells is one use of XY + XY′ = X.

Minterms of the expression

ABC → m(7)

A′C → m(1, 3)

A′B′C′ → m(0)

Group and read off

F = BC + A′B′

Count the literals

L = 4

Answer

L = 4

4.Digital logic: gates, K-maps & flip-flops

Answer: N = 4

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at f_clk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Q after every edge

A JK flip-flop: 00 holds, 01 resets (Q = 0), 10 sets (Q = 1), 11 toggles.

1: J = 1, K = 0 → Q = 1

2: J = 1, K = 1 → Q = 0

3: J = 0, K = 0 → Q = 0

4: J = 1, K = 0 → Q = 1

5: J = 0, K = 0 → Q = 1

6: J = 0, K = 1 → Q = 0

Count the changes

0 → 1 → 0 → 0 → 1 → 1 → 0

N = 4

Answer

N = 4

5.Data acquisition & sampling

Answer: D = 2521

ADC resolution: an N-bit converter divides its full-scale range V_FSR into 2ᴺ codes, from 0 to 2ᴺ − 1. One step is 1 LSB = V_FSR/2ᴺ: the smallest change the converter can show. A truncating ADC gives the code ⌊V_in/LSB⌋; a rounding ADC is never more than ½ LSB away from the true value, its quantisation error. Every extra bit halves the LSB and adds about 6 dB to the ideal signal-to-quantisation-noise ratio SQNR = 6.02·N + 1.76 dB for a full-scale sine. To reach a resolution r over a span, choose the smallest N with 2ᴺ ≥ span/r.

Step size

1 LSB = 2.5/2¹² = 0.6104 mV

Code

V_in/LSB = 1539/0.6104 = 2521

code = ⌊2521⌋ = 2521

Answer

D = 2521

In binary that is 100111011001.

6.Data acquisition & sampling

Answer: e = 8.507 %

UART: an asynchronous serial link sends each byte as a frame: one start bit (low), the data bits, an optional parity bit and one or two stop bits (high). The baud rate is the number of bits per second, so one bit lasts T_b = 1/baud and a frame of n bits lasts n/baud. The common 8N1 format has 10 bits per byte. The baud generator divides the clock: baud = f_clk/(16·D) with a whole number D, so the real baud rate differs slightly from the target; an error below about 2 % is usually acceptable.

Divider

D = 4·10⁶/(16·115200) = 2.17 → 2

Real baud rate

4·10⁶/(16·2) = 125000 Bd

Error

(125000 − 115200)/115200·100 = 8.507 %

Answer

e = 8.507 %

An error above about 2 % makes the link unreliable: choose another clock or baud rate.

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