Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

New problemsBack to the course

In the print window, choose “Save as PDF” to keep a copy on your device.

1Formulas and methods

Number systems

Place values
binary 2k, octal 8k, hex 16k
To decimal
Σ dk·bk
From decimal
divide by the base, read the remainders bottom-up
Hex ↔ binary
one hex digit = 4 bits
Two’s complement
invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion
fs > 2·fmax, fN = fs/2
Alias frequency
fa = |f − k·fs|, k = round(f/fs)
Step size
1 LSB = VFSR/2ᴺ
Quantisation error (rounding)
±½ LSB
Truncating ADC code
D = ⌊Vin/LSB⌋
Bits for a resolution r
2ᴺ ≥ span/r
Ideal SQNR, full-scale sine
SQNR = 6.02·N + 1.76 dB
Data rate
channels × fs × N bit/s
Multiplexed ADC
fs = 1/(n·(tc + tset))
UART
Tb = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider
baud = fclk/(16·D)

Method

  1. Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
  2. For sampling questions, compare each frequency with fs/2; a higher frequency appears at fa = |f − k·fs| with the nearest multiple of fs.
  3. For resolution questions, find 1 LSB = VFSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
  4. For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium
place values in two's complement0−12816403211618140201

The 8-bit pattern 0101 1100 stores a signed integer in two's complement. What is its value N in decimal?

0101 11008 bit
N =
2.Number systemsHard
click the bits to set them012806403201608040201

Set the bits to the 8-bit result of 0111 0110 OR 1111 0101. What is the result's value R in decimal?

0111 0110OR1111 0101
R =
3.Digital logic: gates, K-maps & flip-flopsMedium
ABCD0001111000011110111111

In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.

F = Σm(3, 5, 12, 13, 14, 15)
  1. 1AB = 00, CD = 00
  2. 2AB = 00, CD = 01
  3. 3AB = 00, CD = 11
  4. 4AB = 00, CD = 10
  5. 5AB = 01, CD = 00
  6. 6AB = 01, CD = 01
  7. 7AB = 01, CD = 11
  8. 8AB = 01, CD = 10
  9. 9AB = 11, CD = 00
  10. 10AB = 11, CD = 01
  11. 11AB = 11, CD = 11
  12. 12AB = 11, CD = 10
  13. 13AB = 10, CD = 00
  14. 14AB = 10, CD = 01
  15. 15AB = 10, CD = 11
  16. 16AB = 10, CD = 10
4.Digital logic: gates, K-maps & flip-flopsHard
DQ3​Q3​DQ2​Q2​DQ1​Q1​DQ0​Q0​CLKJOHNSON

A 4-bit Johnson counter Q₃Q₂Q₁Q₀ starts at 0000. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀) and Q₃ receives the inverse of Q₀. Give the state Q = Q₃Q₂Q₁Q₀ as a decimal number after 9 clock edges.

Q₃Q₂Q₁Q₀ = 00009
Q =
5.Data acquisition & samplingMedium
Vin​N = ?500 mm2ᴺ − 10≤ 0.1 mm

A sensor measures distance over a span of 500 mm, and its output fills the whole input range of an ADC. The reading must resolve 0.1 mm. Find the smallest number of bits N the ADC needs.

span = 500 mmresolution = 0.1 mm
N =
6.Data acquisition & samplingHard
T20 mV/°C×2.5∿01N = 10, 3.3 V? °C/LSB

A temperature sensor gives 20 mV/°C (0 V at 0 °C). Its signal is amplified 2.5 times and fed to a 10-bit ADC with a range of 0 to 3.3 V (1 LSB = VFSR/2ᴺ). Find the temperature change ΔTLSB that corresponds to one LSB.

S = 20 mV/°CG = 2.5N = 10VFSR = 3.3 V
ΔTLSB = °C

3Solutions

1.Number systems

Answer: N = 92

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Add the place values

The other bits keep their normal positive values.

64 + 16 + 8 + 4 = 92

Answer

N = 92
2.Number systems

Answer: R = 247

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Bit by bit

OR gives 1 where at least one bit is 1.

0111 0110
OR 1111 0101
= 1111 0111

Value of the result

1111 0111₂ = 247

Answer

R = 247
3.Digital logic: gates, K-maps & flip-flops

Answer: AB = 00, CD = 11

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Neighbours of each 1

A 1 with a neighbouring 1 can join a group of two or more.

m3: m2, m1, m7, m11 → 0
ABCD0001111000011110111111

The isolated 1

m3 = A′B′CD → AB = 00, CD = 11

Answer

AB = 00, CD = 11
4.Digital logic: gates, K-maps & flip-flops

Answer: Q = 8

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

State after every edge

0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000 → 1000

Decimal value

1000₂ = 8

Answer

Q = 8
5.Data acquisition & sampling

Answer: N = 13

ADC resolution: an N-bit converter divides its full-scale range VFSR into 2ᴺ codes, from 0 to 2ᴺ − 1. One step is 1 LSB = VFSR/2ᴺ: the smallest change the converter can show. A truncating ADC gives the code ⌊Vin/LSB⌋; a rounding ADC is never more than ½ LSB away from the true value, its quantisation error. Every extra bit halves the LSB and adds about 6 dB to the ideal signal-to-quantisation-noise ratio SQNR = 6.02·N + 1.76 dB for a full-scale sine. To reach a resolution r over a span, choose the smallest N with 2ᴺ ≥ span/r.

Steps needed

500/0.1 = 5000

Bits

log₂(5000) = 12.29
212 = 4096 < 5000 ≤ 213 = 8192
N = 13

Answer

N = 13
6.Data acquisition & sampling

Answer: ΔTLSB = 0.06445 °C

ADC resolution: an N-bit converter divides its full-scale range VFSR into 2ᴺ codes, from 0 to 2ᴺ − 1. One step is 1 LSB = VFSR/2ᴺ: the smallest change the converter can show. A truncating ADC gives the code ⌊Vin/LSB⌋; a rounding ADC is never more than ½ LSB away from the true value, its quantisation error. Every extra bit halves the LSB and adds about 6 dB to the ideal signal-to-quantisation-noise ratio SQNR = 6.02·N + 1.76 dB for a full-scale sine. To reach a resolution r over a span, choose the smallest N with 2ᴺ ≥ span/r.

Step size

1 LSB = 3300/1024 = 3.223 mV

Sensitivity at the ADC

20·2.5 = 50 mV/°C

Temperature resolution

ΔTLSB = 3.223/50 = 0.06445 °C

Answer

ΔTLSB = 0.06445 °C

The ADC reaches full scale at 66 °C.

ExamProblems · examproblems.com/courses/digital-electronics