Number systems
- Place values
- binary 2k, octal 8k, hex 16k
- To decimal
- Σ dk·bk
- From decimal
- divide by the base, read the remainders bottom-up
- Hex ↔ binary
- one hex digit = 4 bits
- Two’s complement
- invert the bits and add 1
Digital Electronics: cram pack
Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.
1Formulas and methods
Digital logic: gates, K-maps & flip-flops
- Basic gates
- A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
- Boolean rules
- X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
- De Morgan
- (X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
- Karnaugh map order
- 00, 01, 11, 10 (Gray code)
- Group of 2ᵏ cells
- loses k variables
- 4-to-1 multiplexer
- F = A′B′I0 + A′BI1 + AB′I2 + ABI3
- Flip-flops
- D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
- Counters
- n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
- Ripple counter
- fmax = 1/(n·tpd)
- Ring and Johnson counters
- n and 2n states
Method
- For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
- For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
- Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
- For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
Data acquisition & sampling
- Nyquist criterion
- fs > 2·fmax, fN = fs/2
- Alias frequency
- fa = |f − k·fs|, k = round(f/fs)
- Step size
- 1 LSB = VFSR/2ᴺ
- Quantisation error (rounding)
- ±½ LSB
- Truncating ADC code
- D = ⌊Vin/LSB⌋
- Bits for a resolution r
- 2ᴺ ≥ span/r
- Ideal SQNR, full-scale sine
- SQNR = 6.02·N + 1.76 dB
- Data rate
- channels × fs × N bit/s
- Multiplexed ADC
- fs = 1/(n·(tc + tset))
- UART
- Tb = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
- Baud rate divider
- baud = fclk/(16·D)
Method
- Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
- For sampling questions, compare each frequency with fs/2; a higher frequency appears at fa = |f − k·fs| with the nearest multiple of fs.
- For resolution questions, find 1 LSB = VFSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
- For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.
2Practice problems
1.Number systemsMedium
Set the bits so they store −29 in 8-bit two's complement. Read as an unsigned number, what is the pattern's value U?
N = −298 bit
U =
2.Number systemsHard
What is the most negative integer N that can be stored in 32-bit two's complement?
32 bit
N =
3.Digital logic: gates, K-maps & flip-flopsMedium
A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = C, I₁ = C, I₂ = C, I₃ = 1. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.
I₀ = CI₁ = CI₂ = CI₃ = 1
N =
4.Digital logic: gates, K-maps & flip-flopsHard
A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown at 7 rising clock edges. How many times N does Q change state?
Q₀ = 0JK
N =
5.Data acquisition & samplingMedium
A recorder samples 4 channels at 2 kHz each with a 14-bit ADC. Each sample is stored in whole bytes. Find the memory M needed for a 60 min recording, in MB (1 MB = 10⁶ bytes).
n = 4fs = 2 kHzN = 14t = 60 min
M = MB
6.Data acquisition & samplingHard
A 6-channel multiplexer feeds one ADC. Each conversion takes 8 µs, and after every channel switch the input needs 5 µs to settle. The channels are scanned in turn without pause. Find the sampling rate fs of each channel, in kHz.
n = 6tc = 8 µstset = 5 µs
fs = kHz
3Solutions
1.Number systems
Answer: U = 227
Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.
Invert and add one
29 = 0001 1101
inverted: 1110 0010
+1 → 1110 0011
Read it as unsigned
1110 0011₂ = 256 − 29 = 227
Answer
U = 227
2.Number systems
Answer: N = −2.147 × 10⁹
Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.
Most negative value
−231 = −2147483648
Answer
N = −2147483648
3.Digital logic: gates, K-maps & flip-flops
Answer: N = 5
Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.
Output expression
F = A′B′C + A′BC + AB′C + AB
Rows with F = 1
ABC = 001, 011, 101, 110, 111
N = 5
Answer
N = 5
4.Digital logic: gates, K-maps & flip-flops
Answer: N = 3
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
Q after every edge
A JK flip-flop: 00 holds, 01 resets (Q = 0), 10 sets (Q = 1), 11 toggles.
1: J = 1, K = 1 → Q = 1
2: J = 0, K = 0 → Q = 1
3: J = 1, K = 0 → Q = 1
4: J = 0, K = 0 → Q = 1
5: J = 0, K = 0 → Q = 1
6: J = 1, K = 1 → Q = 0
7: J = 1, K = 0 → Q = 1
Count the changes
0 → 1 → 1 → 1 → 1 → 1 → 0 → 1
N = 3
Answer
N = 3
5.Data acquisition & sampling
Answer: M = 57.6 MB
Data rates: every channel delivers fs samples per second of N bits, so the raw rate is channels × fs × N bit/s. In memory a sample takes whole bytes (a 12-bit sample is stored in 2 bytes), so the memory for a recording is channels × fs × bytes per sample × time. A multiplexed ADC converts the channels one after another: each conversion (with settling) takes t, so one round of n channels takes n·t and each channel is sampled at 1/(n·t).
Bytes per sample
⌈14/8⌉ = 2 B
Byte rate
4·2000·2 = 16000 B/s
Memory
M = 16000·3600 = 5.76 × 10⁷ B = 57.6 MB
Answer
M = 57.6 MB
6.Data acquisition & sampling
Answer: fs = 12.82 kHz
Data rates: every channel delivers fs samples per second of N bits, so the raw rate is channels × fs × N bit/s. In memory a sample takes whole bytes (a 12-bit sample is stored in 2 bytes), so the memory for a recording is channels × fs × bytes per sample × time. A multiplexed ADC converts the channels one after another: each conversion (with settling) takes t, so one round of n channels takes n·t and each channel is sampled at 1/(n·t).
Time per channel
8 + 5 = 13 µs
Time per scan
6·13 = 78 µs
Sampling rate per channel
fs = 1/78 µs = 12.82 kHz
Answer
fs = 12.82 kHz
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