Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

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1Formulas and methods

Number systems

Place values
binary 2k, octal 8k, hex 16k
To decimal
Σ dk·bk
From decimal
divide by the base, read the remainders bottom-up
Hex ↔ binary
one hex digit = 4 bits
Two’s complement
invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion
fs > 2·fmax, fN = fs/2
Alias frequency
fa = |f − k·fs|, k = round(f/fs)
Step size
1 LSB = VFSR/2ᴺ
Quantisation error (rounding)
±½ LSB
Truncating ADC code
D = ⌊Vin/LSB⌋
Bits for a resolution r
2ᴺ ≥ span/r
Ideal SQNR, full-scale sine
SQNR = 6.02·N + 1.76 dB
Data rate
channels × fs × N bit/s
Multiplexed ADC
fs = 1/(n·(tc + tset))
UART
Tb = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider
baud = fclk/(16·D)

Method

  1. Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
  2. For sampling questions, compare each frequency with fs/2; a higher frequency appears at fa = |f − k·fs| with the nearest multiple of fs.
  3. For resolution questions, find 1 LSB = VFSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
  4. For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium
8-bit two's complement0−12806403201608040201

Set the bits so they store −53 in 8-bit two's complement. Read as an unsigned number, what is the pattern's value U?

N = −538 bit
U =
2.Number systemsHard
click the bits to set them012806403201608040201

Set the bits to the 8-bit result of 0100 1011 XOR 0111 0110. What is the result's value R in decimal?

0100 1011XOR0111 0110
R =
3.Digital logic: gates, K-maps & flip-flopsMedium
ABCD000111100001111000011302140517060121131150140809111110

Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C, D) = Σm(3, 4, 7, 10, 11, 13, 15). How many literals L does it contain in total (a primed variable counts as one literal)?

F(A, B, C, D) = Σm(3, 4, 7, 10, 11, 13, 15)
L =
4.Digital logic: gates, K-maps & flip-flopsHard
ABCD00011110000111101001030204051706X12113015X140809111110

For F(A, B, C, D) = Σm(0, 7, 10, 11, 13) + d(12, 14), where d marks the don't-care conditions, find the number N of essential prime implicants.

F(A, B, C, D) = Σm(0, 7, 10, 11, 13) + d(12, 14)
N =
5.Data acquisition & samplingMedium
Vin​N = 16VFSR​2ᴺ − 101 LSB

Find the ideal signal-to-quantisation-noise ratio SQNR of a 16-bit ADC for a full-scale sine wave.

N = 16
SQNR = dB
6.Data acquisition & samplingHard
SD0​D1​D2​D3​D4​D5​D6​D7​PTb​11·Tb​57600 Bd, 8E1

A 12-bit ADC streams every sample over a UART at 57600 baud, format 8E1 (start bit, 8 data bits, even parity, 1 stop bit). Each sample is sent as 2 whole byte(s) and the link is busy all the time. Find the highest signal frequency fmax that can be sampled without aliasing, in Hz.

baud = 57600 BdN = 128E1
fmax = Hz

3Solutions

1.Number systems

Answer: U = 203

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Invert and add one

53 = 0011 0101
inverted: 1100 1010
+1 → 1100 1011

Read it as unsigned

1100 1011₂ = 256 − 53 = 203

Answer

U = 203
2.Number systems

Answer: R = 61

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Bit by bit

XOR gives 1 where the two bits differ.

0100 1011
XOR 0111 0110
= 0011 1101

Value of the result

0011 1101₂ = 61

Answer

R = 61
3.Digital logic: gates, K-maps & flip-flops

Answer: L = 12

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

ABCD000111100001111000011302140517060121131150140809111110

Group the 1s

Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.

CD
ABD
AB′C
A′BC′D′

Minimal SOP form

F = CD + ABD + AB′C + A′BC′D′
L = 12

Answer

L = 12
4.Digital logic: gates, K-maps & flip-flops

Answer: N = 4

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Prime implicants

The largest groups that can be formed from 1s and Xs.

ACD′, AB′C, ABC′, A′B′C′D′, A′BCD
ABCD00011110000111101001030204051706X12113015X140809111110

Essential prime implicants

AB′C, ABC′, A′B′C′D′, A′BCD
N = 4

Answer

N = 4
5.Data acquisition & sampling

Answer: SQNR = 98.08 dB

ADC resolution: an N-bit converter divides its full-scale range VFSR into 2ᴺ codes, from 0 to 2ᴺ − 1. One step is 1 LSB = VFSR/2ᴺ: the smallest change the converter can show. A truncating ADC gives the code ⌊Vin/LSB⌋; a rounding ADC is never more than ½ LSB away from the true value, its quantisation error. Every extra bit halves the LSB and adds about 6 dB to the ideal signal-to-quantisation-noise ratio SQNR = 6.02·N + 1.76 dB for a full-scale sine. To reach a resolution r over a span, choose the smallest N with 2ᴺ ≥ span/r.

Ideal SQNR

SQNR = 6.02·16 + 1.76 = 98.08 dB

Answer

SQNR = 98.08 dB
6.Data acquisition & sampling

Answer: fmax = 1309 Hz

UART: an asynchronous serial link sends each byte as a frame: one start bit (low), the data bits, an optional parity bit and one or two stop bits (high). The baud rate is the number of bits per second, so one bit lasts Tb = 1/baud and a frame of n bits lasts n/baud. The common 8N1 format has 10 bits per byte. The baud generator divides the clock: baud = fclk/(16·D) with a whole number D, so the real baud rate differs slightly from the target; an error below about 2 % is usually acceptable.

Bits per sample on the line

2·11 = 22 bit

Highest sampling rate

fs,max = 57600/22 = 2618 Hz

Nyquist limit

fmax = 2618/2 = 1309 Hz

Answer

fmax = 1309 Hz

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