Digital Electronics: cram pack

Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.

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1Formulas and methods

Number systems

Place values: binary 2^k, octal 8^k, hex 16^k
To decimal: Σ d_k·b^k
From decimal: divide by the base, read the remainders bottom-up
Hex ↔ binary: one hex digit = 4 bits
Two’s complement: invert the bits and add 1

Digital logic: gates, K-maps & flip-flops

Basic gates: A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules: X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan: (X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order: 00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells: loses k variables
4-to-1 multiplexer: F = A′B′I₀ + A′BI₁ + AB′I₂ + ABI₃
Flip-flops: D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters: n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; f_out = f_clk/N
Ripple counter: f_max = 1/(n·t_pd)
Ring and Johnson counters: n and 2n states

Method

For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

Data acquisition & sampling

Nyquist criterion: f_s > 2·f_max, f_N = f_s/2
Alias frequency: f_a = |f − k·f_s|, k = round(f/f_s)
Step size: 1 LSB = V_FSR/2ᴺ
Quantisation error (rounding): ±½ LSB
Truncating ADC code: D = ⌊V_in/LSB⌋
Bits for a resolution r: 2ᴺ ≥ span/r
Ideal SQNR, full-scale sine: SQNR = 6.02·N + 1.76 dB
Data rate: channels × f_s × N bit/s
Multiplexed ADC: f_s = 1/(n·(t_c + t_set))
UART: T_b = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
Baud rate divider: baud = f_clk/(16·D)

Method

Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
For sampling questions, compare each frequency with f_s/2; a higher frequency appears at f_a = |f − k·f_s| with the nearest multiple of f_s.
For resolution questions, find 1 LSB = V_FSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.

2Practice problems

1.Number systemsMedium

The 8-bit pattern 1011 0111 stores a signed integer in two's complement. What is its value N in decimal?

1011 01118 bit

N =

2.Number systemsHard

Set the bits to the 8-bit result of 1110 1000 XOR 1011 1100. What is the result's value R in decimal?

1110 1000XOR1011 1100

R =

3.Digital logic: gates, K-maps & flip-flopsMedium

A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = 1, I₁ = C, I₂ = 0, I₃ = C. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.

I₀ = 1I₁ = CI₂ = 0I₃ = C

N =

4.Digital logic: gates, K-maps & flip-flopsHard

A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.

Q₀ = 0JK

1clock edge 1
2clock edge 2
3clock edge 3
4clock edge 4
5clock edge 5
6clock edge 6
7clock edge 7

5.Data acquisition & samplingMedium

A 12-bit ADC with an input range of 0 to 10 V truncates: its output code is ⌊V_in/LSB⌋ with 1 LSB = V_FSR/2ᴺ. Find the decimal output code D for an input of 2.858 V.

N = 12V_FSR = 10 VV_in = 2.858 V

D =

6.Data acquisition & samplingHard

An 8-channel multiplexer feeds one ADC. Each conversion takes 4 µs, and after every channel switch the input needs 2 µs to settle. The channels are scanned in turn without pause. Find the sampling rate f_s of each channel, in kHz.

n = 8t_c = 4 µst_set = 2 µs

f_s = kHz

3Solutions

1.Number systems

Answer: N = −73

Positional number systems: each digit is worth its value times a power of the base. In binary the places are worth 1, 2, 4, 8, 16, …; in hexadecimal 1, 16, 256, …, with A–F standing for 10–15. In 8-bit two's complement the leftmost bit is worth −128 instead of +128, which is how negative numbers are stored.

Add the place values

The other bits keep their normal positive values.

−128 + 32 + 16 + 4 + 2 + 1 = −73

Answer

N = −73

2.Number systems

Answer: R = 84

Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.

Bit by bit

XOR gives 1 where the two bits differ.

1110 1000

XOR 1011 1100

= 0101 0100

Value of the result

0101 0100₂ = 84

Answer

R = 84

3.Digital logic: gates, K-maps & flip-flops

Answer: N = 4

Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.

Output expression

F = A′B′ + A′BC + ABC

Rows with F = 1

ABC = 000, 001, 011, 111

N = 4

Answer

N = 4

4.Digital logic: gates, K-maps & flip-flops

Answer: clock edge 4

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at f_clk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Q after every edge

A JK flip-flop: 00 holds, 01 resets (Q = 0), 10 sets (Q = 1), 11 toggles.

1: J = 0, K = 0 → Q = 0

2: J = 1, K = 0 → Q = 1

3: J = 1, K = 0 → Q = 1

4: J = 0, K = 1 → Q = 0

5: J = 0, K = 1 → Q = 0

6: J = 1, K = 0 → Q = 1

7: J = 0, K = 0 → Q = 1

First change from 1 to 0

clock edge 4

Answer

clock edge 4

5.Data acquisition & sampling

Answer: D = 1170

ADC resolution: an N-bit converter divides its full-scale range V_FSR into 2ᴺ codes, from 0 to 2ᴺ − 1. One step is 1 LSB = V_FSR/2ᴺ: the smallest change the converter can show. A truncating ADC gives the code ⌊V_in/LSB⌋; a rounding ADC is never more than ½ LSB away from the true value, its quantisation error. Every extra bit halves the LSB and adds about 6 dB to the ideal signal-to-quantisation-noise ratio SQNR = 6.02·N + 1.76 dB for a full-scale sine. To reach a resolution r over a span, choose the smallest N with 2ᴺ ≥ span/r.

Step size

1 LSB = 10/2¹² = 2.441 mV

Code

V_in/LSB = 2858/2.441 = 1171

code = ⌊1171⌋ = 1170

Answer

D = 1170

In binary that is 010010010010.

6.Data acquisition & sampling

Answer: f_s = 20.83 kHz

Data rates: every channel delivers f_s samples per second of N bits, so the raw rate is channels × f_s × N bit/s. In memory a sample takes whole bytes (a 12-bit sample is stored in 2 bytes), so the memory for a recording is channels × f_s × bytes per sample × time. A multiplexed ADC converts the channels one after another: each conversion (with settling) takes t, so one round of n channels takes n·t and each channel is sampled at 1/(n·t).

Time per channel

4 + 2 = 6 µs

Time per scan

8·6 = 48 µs

Sampling rate per channel

f_s = 1/48 µs = 20.83 kHz

Answer

f_s = 20.83 kHz

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