Number systems
- Place values
- binary 2k, octal 8k, hex 16k
- To decimal
- Σ dk·bk
- From decimal
- divide by the base, read the remainders bottom-up
- Hex ↔ binary
- one hex digit = 4 bits
- Two’s complement
- invert the bits and add 1
Digital Electronics: cram pack
Formula sheets, the key method steps for every topic and 6 practice problems, with full solutions at the back.
1Formulas and methods
Digital logic: gates, K-maps & flip-flops
- Basic gates
- A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
- Boolean rules
- X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
- De Morgan
- (X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
- Karnaugh map order
- 00, 01, 11, 10 (Gray code)
- Group of 2ᵏ cells
- loses k variables
- 4-to-1 multiplexer
- F = A′B′I0 + A′BI1 + AB′I2 + ABI3
- Flip-flops
- D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
- Counters
- n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
- Ripple counter
- fmax = 1/(n·tpd)
- Ring and Johnson counters
- n and 2n states
Method
- For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
- For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
- Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
- For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
Data acquisition & sampling
- Nyquist criterion
- fs > 2·fmax, fN = fs/2
- Alias frequency
- fa = |f − k·fs|, k = round(f/fs)
- Step size
- 1 LSB = VFSR/2ᴺ
- Quantisation error (rounding)
- ±½ LSB
- Truncating ADC code
- D = ⌊Vin/LSB⌋
- Bits for a resolution r
- 2ᴺ ≥ span/r
- Ideal SQNR, full-scale sine
- SQNR = 6.02·N + 1.76 dB
- Data rate
- channels × fs × N bit/s
- Multiplexed ADC
- fs = 1/(n·(tc + tset))
- UART
- Tb = 1/baud; 8N1 = 10 bits per byte; bytes/s = baud/bits per frame
- Baud rate divider
- baud = fclk/(16·D)
Method
- Write down what is given: sampling rate, signal frequencies, number of bits, input range, baud rate.
- For sampling questions, compare each frequency with fs/2; a higher frequency appears at fa = |f − k·fs| with the nearest multiple of fs.
- For resolution questions, find 1 LSB = VFSR/2ᴺ, or the smallest N with 2ᴺ ≥ span/resolution.
- For data rates and UART links, count everything that is sent: channels, samples per second, bits or whole bytes per sample, and the start, parity and stop bits of every frame.
2Practice problems
1.Number systemsMedium
Set the bits so they store −42 in 8-bit two's complement. Read as an unsigned number, what is the pattern's value U?
N = −428 bit
U =
2.Number systemsHard
Set the bits to the 8-bit result of 1110 0101 AND 0100 1110. What is the result's value R in decimal?
1110 0101AND0100 1110
R =
3.Digital logic: gates, K-maps & flip-flopsMedium
A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = C, I₁ = C, I₂ = 0, I₃ = 0. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.
I₀ = CI₁ = CI₂ = 0I₃ = 0
N =
4.Digital logic: gates, K-maps & flip-flopsHard
A 4-bit Johnson counter Q₃Q₂Q₁Q₀ starts at 0000. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀) and Q₃ receives the inverse of Q₀. Give the state Q = Q₃Q₂Q₁Q₀ as a decimal number after 10 clock edges.
Q₃Q₂Q₁Q₀ = 000010
Q =
5.Data acquisition & samplingMedium
Find the ideal signal-to-quantisation-noise ratio SQNR of a 20-bit ADC for a full-scale sine wave.
N = 20
SQNR = dB
6.Data acquisition & samplingHard
A 3 kHz square wave is sampled at 20 kHz with no anti-aliasing filter. A square wave contains the odd harmonics 3f₁, 5f₁, 7f₁, … At which frequency fa does its harmonic 7f₁ appear in the sampled data? Give it in kHz.
f₁ = 3 kHzfs = 20 kHzharmonic: 7f₁
fa = kHz
3Solutions
1.Number systems
Answer: U = 214
Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.
Invert and add one
42 = 0010 1010
inverted: 1101 0101
+1 → 1101 0110
Read it as unsigned
1101 0110₂ = 256 − 42 = 214
Answer
U = 214
2.Number systems
Answer: R = 68
Setting bits: each bit is worth a power of two (128, 64, …, 1). One hex digit is exactly four bits, and in 8-bit two's complement the leftmost bit is worth −128. Bitwise operations work on each bit position separately.
Bit by bit
AND gives 1 only where both bits are 1.
1110 0101
AND 0100 1110
= 0100 0100
Value of the result
0100 0100₂ = 68
Answer
R = 68
3.Digital logic: gates, K-maps & flip-flops
Answer: N = 2
Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.
Output expression
F = A′B′C + A′BC
Rows with F = 1
ABC = 001, 011
N = 2
Answer
N = 2
4.Digital logic: gates, K-maps & flip-flops
Answer: Q = 12
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
State after every edge
0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000 → 1000 → 1100
Decimal value
1100₂ = 12
Answer
Q = 12
5.Data acquisition & sampling
Answer: SQNR = 122.2 dB
ADC resolution: an N-bit converter divides its full-scale range VFSR into 2ᴺ codes, from 0 to 2ᴺ − 1. One step is 1 LSB = VFSR/2ᴺ: the smallest change the converter can show. A truncating ADC gives the code ⌊Vin/LSB⌋; a rounding ADC is never more than ½ LSB away from the true value, its quantisation error. Every extra bit halves the LSB and adds about 6 dB to the ideal signal-to-quantisation-noise ratio SQNR = 6.02·N + 1.76 dB for a full-scale sine. To reach a resolution r over a span, choose the smallest N with 2ᴺ ≥ span/r.
Ideal SQNR
SQNR = 6.02·20 + 1.76 = 122.2 dB
Answer
SQNR = 122.2 dB
6.Data acquisition & sampling
Answer: fa = 1 kHz
Sampling: an ADC measures the signal fs times per second. By the Nyquist–Shannon theorem a frequency f is captured correctly only while f < fs/2, the Nyquist (folding) frequency, so the sampling rate must exceed twice the highest signal frequency. A higher frequency is not lost: it shows up as an alias at fa = |f − k·fs|, with the whole number k that brings the result between 0 and fs/2. The samples cannot tell the two apart, so an analogue anti-aliasing filter must remove everything above fs/2 before the ADC.
Harmonic frequency
7f₁ = 7·3 kHz = 21 kHz
Nearest multiple of the sampling rate
m = round(1.05) = 1
Alias frequency
fa = |21 − 1·20| = 1 kHz
Answer
fa = 1 kHz
The alias lands inside the signal band, where no digital filter can remove it. Only an analogue filter before the ADC helps.
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