Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
A 5.6 V Zener regulator is fed from 20 V through 220 Ω and supplies a 2200 Ω load. Find the Zener current IZ.
Vin = 20 VVZ = 5.6 VR = 220 ΩRL = 2200 Ω
IZ = mA
2.Diodes & transistorsHard
An NPN transistor with β = 50 switches a 100 Ω load resistor connected between VCC = 24 V and its collector. The emitter is grounded. The base is driven from a 3.3 V logic output through a base resistor RB. Take VBE = 0.7 V and VCE(sat) = 0.2 V. For reliable switching, design for a base current 10 times the minimum needed for saturation. Find RB in kΩ.
The op-amp is ideal and runs from ±15 V supplies. Find the output voltage Vout.
Vin = −1.6 VR1 = 4.7 kΩRf = 22 kΩ
Vout = V
4.Op-amp circuitsHard
The summing amplifier uses an ideal op-amp with ±15 V supplies. Find the output voltage Vout.
V1 = 0.3 VV2 = 0.3 VR1 = 47 kΩR2 = 1 kΩRf = 2 kΩ
Vout = V
5.RC & RL transientsMedium
The source Vₛ charges the capacitor through R₁, and R₂ is connected in parallel with C. The capacitor is uncharged when the switch closes at t = 0. Find the capacitor voltage vC at t = 25 ms.
Vs = 10 VR1 = 4.7 kΩR2 = 1 kΩC = 47 µFt = 25 ms
vC = V
6.RC & RL transientsHard
The switch has been closed for a long time, so the circuit is in steady state. At t = 0 the switch opens. Find the capacitor voltage vC at t = 50 ms.
Vs = 10 VR1 = 1 kΩR2 = 2.2 kΩC = 47 µFt = 50 ms
vC = V
7.Series & parallel resistorsMedium
Find the current IR2 through R2.
V1 = 30 VR1 = 4 ΩR2 = 6 ΩR3 = 4 ΩR4 = 8 Ω
IR2 = A
8.Series & parallel resistorsHard
Find the equivalent resistance Req seen by the source V1.
An ideal boost converter turns 12 V into 20 V for a 15 Ω load. Find the average inductor current IL.
Vin = 12 VVo = 20 VR = 15 Ω
IL = A
10.DC-DC convertersHard
An ideal buck-boost converter turns 9 V into −9 V for a 4 Ω load at 50 kHz. The output capacitor is 220 µF. Find the peak-to-peak output voltage ripple ΔVo in mV.
Vin = 9 VVo = −9 Vf = 50 kHzC = 220 µFR = 4 Ω
ΔVo = mV
11.Wheatstone bridge & strain gaugesMedium
A 330 Ω strain gauge is one arm (R₂) of a bridge with four equal 330 Ω arms and an excitation of 5 V. Find the power Pg dissipated in the gauge, in mW. Self-heating limits the excitation.
Vs = 5 VR = 330 Ω
Pg = mW
12.Wheatstone bridge & strain gaugesHard
A load cell (a full bridge of strain gauges) has a rated output of 1.5 mV/V at its rated load of 1000 kg. It is excited with 10 V. Find its output Vo under a load of 800 kg.
A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = 1, I₁ = C′, I₂ = C′, I₃ = C′. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.
I₀ = 1I₁ = C′I₂ = C′I₃ = C′
N =
14.Digital logic: gates, K-maps & flip-flopsHard
Find the minimal SOP form of F(A, B, C, D) = Σm(2, 5, 12, 15) + d(6, 10, 13), where d marks the don't-care conditions. How many literals L does it contain?
F(A, B, C, D) = Σm(2, 5, 12, 15) + d(6, 10, 13)
L =
3Solutions
1.Diodes & transistors
Answer: IZ = 62.91 mA
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Resistor current
IR = 14.4/220 = 65.45 mA
Load current
IL = 5.6/2200 = 2.545 mA
Zener current
IZ = 65.45 − 2.545 = 62.91 mA
Answer
IZ = 62.91 mA
2.Diodes & transistors
Answer: RB = 0.05462 kΩ
BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.
Collector current in saturation
IC(sat) = (24 − 0.2)/100 = 238 mA
Minimum base current
IB(min) = IC(sat)/β = 238/50 = 4760 µA
Design base current
IB = 10·4760 µA = 47600 µA
Base resistor
RB = (3.3 − 0.7)/IB = 2.6 V/47.6 mA = 0.05462 kΩ
Answer
RB = 0.05462 kΩ
3.Op-amp circuits
Answer: Vout = −9.089 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Inverting input follows the input
V₋ = V₊ = −1.6 V
I = V₋/R1 = −1.6/4.7 = −0.3404 mA
Output voltage
The current through R₁ also flows through Rf.
Vout = V₋ + I·Rf = −1.6 + (−0.3404)·22 = −9.089 V
Answer
Vout = −9.089 V
4.Op-amp circuits
Answer: Vout = −0.6128 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Input currents
V₋ = 0, so each input resistor has its full input voltage across it.
I1 = V1/R1 = 0.3/47 = 0.006383 mA
I2 = V2/R2 = 0.3/1 = 0.3 mA
If = I1 + I2 = 0.3064 mA
Output voltage
Vout = −Rf·If = −2·0.3064 = −0.6128 V
Answer
Vout = −0.6128 V
5.RC & RL transients
Answer: vC = 0.834 V
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Thévenin equivalent seen by the capacitor
Short the source to find Rth; open the capacitor to find the voltage it will settle at.
Rth = R1 ∥ R2 = 4.7·1/(4.7 + 1) = 0.8246 kΩ
vC(∞) = 10·1/(4.7 + 1) = 1.754 V
Time constant
τ = Rth·C = 0.8246·47 = 38.75 ms
Charging curve
vC(t) = 1.754·(1 − e−25/38.75) = 0.834 V
Answer
vC = 0.834 V
6.RC & RL transients
Answer: vC = 4.239 V
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial capacitor voltage
In steady state the capacitor is an open circuit, so R₁ and R₂ form a voltage divider. The capacitor voltage cannot jump when the switch opens.
vC(0) = 10·2.2/(1 + 2.2) = 6.875 V
Time constant after the switch opens
τ = R2·C = 2.2·47 = 103.4 ms
Discharge
vC(t) = 6.875·e−50/103.4 = 4.239 V
Answer
vC = 4.239 V
7.Series & parallel resistors
Answer: IR2 = 2.5 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 4 + 8 = 12 Ω
R2 ∥ 12 = 6·12/(6+12) = 4 Ω
Req = R1 + 4 = 4 + 4 = 8 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 30/8 = 3.75 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 30 − 3.75·4 = 15 V
IR2 = VA/R2 = 15/6 = 2.5 A
Answer
IR2 = 2.5 A
8.Series & parallel resistors
Answer: Req = 8.248 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 15 + 20 = 35 Ω
R4 ∥ 35 = 1.892 Ω
R3 + 1.892 = 7.892 Ω
R2 ∥ 7.892 = 6.248 Ω
Req = R1 + 6.248 = 2 + 6.248 = 8.248 Ω
Answer
Req = 8.248 Ω
9.DC-DC converters
Answer: IL = 2.222 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 1 − 12/20 = 0.4
Load current
Io = 20/15 = 1.333 A
Inductor current
IL = Io/(1 − D) = 1.333/0.6 = 2.222 A
Answer
IL = 2.222 A
10.DC-DC converters
Answer: ΔVo = 102.3 mV
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 9/(9 + 9) = 0.5
Load current
Io = 9/4 = 2.25 A
Output ripple
ΔVo = 2.25·0.5/(50·10³·220·10⁻⁶) = 102.3 mV
Answer
ΔVo = 102.3 mV
11.Wheatstone bridge & strain gauges
Answer: Pg = 18.94 mW
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Voltage across the gauge
V = 5/2 = 2.5 V
Power
Pg = 2.5²/330 = 18.94 mW
Answer
Pg = 18.94 mW
12.Wheatstone bridge & strain gauges
Answer: Vo = 12 mV
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Full-scale output
1.5·10 = 15 mV
Output at this load
Vo = 15·800/1000 = 12 mV
Answer
Vo = 12 mV
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 5
Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.
Output expression
F = A′B′ + A′BC′ + AB′C′ + ABC′
Rows with F = 1
ABC = 000, 001, 010, 100, 110
N = 5
Answer
N = 5
14.Digital logic: gates, K-maps & flip-flops
Answer: L = 12
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Prime implicants
The largest groups that can be formed from 1s and Xs.
B′CD′, BC′D, A′CD′, ABD, ABC′
Minimal cover
F = B′CD′ + BC′D + ABD + ABC′
L = 12
Answer
L = 12
Another grouping of the same size exists; it has the same number of terms and literals.